Angel Pons | a2ee761 | 2020-04-04 18:51:15 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Daisuke Nojiri | 1b05d88 | 2014-08-27 11:48:03 -0700 | [diff] [blame] | 2 | |
| 3 | #include <arch/cache.h> |
Julius Werner | f0d21ff3 | 2014-10-20 13:24:14 -0700 | [diff] [blame] | 4 | #include <soc/cache.h> |
Daisuke Nojiri | 1b05d88 | 2014-08-27 11:48:03 -0700 | [diff] [blame] | 5 | #include <stdint.h> |
Daisuke Nojiri | 1b05d88 | 2014-08-27 11:48:03 -0700 | [diff] [blame] | 6 | |
| 7 | enum { |
| 8 | L2CTLR_ECC_PARITY = 0x1 << 21, |
| 9 | L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6, |
| 10 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6, |
| 11 | L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0, |
| 12 | L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0 |
| 13 | }; |
| 14 | |
| 15 | enum { |
| 16 | L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27, |
| 17 | L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7, |
| 18 | L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3 |
| 19 | }; |
| 20 | |
| 21 | /* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */ |
| 22 | static void configure_l2ctlr(void) |
| 23 | { |
| 24 | uint32_t val; |
| 25 | |
| 26 | val = read_l2ctlr(); |
| 27 | val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK); |
| 28 | val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 | |
| 29 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 | L2CTLR_ECC_PARITY); |
| 30 | write_l2ctlr(val); |
| 31 | } |
| 32 | |
| 33 | /* Configures L2 Auxiliary Control Register for Cortex A15. */ |
| 34 | static void configure_l2actlr(void) |
| 35 | { |
| 36 | uint32_t val; |
| 37 | |
| 38 | val = read_l2actlr(); |
| 39 | val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL | |
| 40 | L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT | |
| 41 | L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE); |
| 42 | write_l2actlr(val); |
| 43 | } |
| 44 | |
| 45 | void configure_l2_cache(void) |
| 46 | { |
| 47 | configure_l2ctlr(); |
| 48 | configure_l2actlr(); |
| 49 | } |