Angel Pons | a2ee761 | 2020-04-04 18:51:15 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Angel Pons | a2ee761 | 2020-04-04 18:51:15 +0200 | [diff] [blame] | 2 | |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 3 | /* |
| 4 | * drivers/video/tegra/dc/dpaux_regs.h |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __SOC_NVIDIA_TEGRA_DISPLAYPORT_H__ |
| 8 | #define __SOC_NVIDIA_TEGRA_DISPLAYPORT_H__ |
| 9 | |
Julius Werner | f0d21ff3 | 2014-10-20 13:24:14 -0700 | [diff] [blame] | 10 | #include <soc/sor.h> |
| 11 | |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 12 | /* things we can't get rid of just yet. */ |
| 13 | #define DPAUX_INTR_EN_AUX (0x1) |
| 14 | #define DPAUX_INTR_AUX (0x5) |
| 15 | #define DPAUX_DP_AUXDATA_WRITE_W(i) (0x9 + 4*(i)) |
| 16 | #define DPAUX_DP_AUXDATA_READ_W(i) (0x19 + 4*(i)) |
| 17 | #define DPAUX_DP_AUXADDR (0x29) |
| 18 | #define DPAUX_DP_AUXCTL (0x2d) |
| 19 | #define DPAUX_DP_AUXCTL_CMDLEN_SHIFT (0) |
| 20 | #define DPAUX_DP_AUXCTL_CMDLEN_FIELD (0xff) |
| 21 | #define DPAUX_DP_AUXCTL_CMD_SHIFT (12) |
| 22 | #define DPAUX_DP_AUXCTL_CMD_MASK (0xf << 12) |
| 23 | #define DPAUX_DP_AUXCTL_CMD_I2CWR (0 << 12) |
| 24 | #define DPAUX_DP_AUXCTL_CMD_I2CRD (1 << 12) |
| 25 | #define DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT (2 << 12) |
| 26 | #define DPAUX_DP_AUXCTL_CMD_MOTWR (4 << 12) |
| 27 | #define DPAUX_DP_AUXCTL_CMD_MOTRD (5 << 12) |
| 28 | #define DPAUX_DP_AUXCTL_CMD_MOTREQWSTAT (6 << 12) |
| 29 | #define DPAUX_DP_AUXCTL_CMD_AUXWR (8 << 12) |
| 30 | #define DPAUX_DP_AUXCTL_CMD_AUXRD (9 << 12) |
| 31 | #define DPAUX_DP_AUXCTL_TRANSACTREQ_SHIFT (16) |
| 32 | #define DPAUX_DP_AUXCTL_TRANSACTREQ_MASK (0x1 << 16) |
| 33 | #define DPAUX_DP_AUXCTL_TRANSACTREQ_DONE (0 << 16) |
| 34 | #define DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING (1 << 16) |
| 35 | #define DPAUX_DP_AUXCTL_RST_SHIFT (31) |
| 36 | #define DPAUX_DP_AUXCTL_RST_DEASSERT (0 << 31) |
| 37 | #define DPAUX_DP_AUXCTL_RST_ASSERT (1 << 31) |
| 38 | #define DPAUX_DP_AUXSTAT (0x31) |
| 39 | #define DPAUX_DP_AUXSTAT_HPD_STATUS_SHIFT (28) |
| 40 | #define DPAUX_DP_AUXSTAT_HPD_STATUS_UNPLUG (0 << 28) |
| 41 | #define DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED (1 << 28) |
| 42 | #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SHIFT (20) |
| 43 | #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_MASK (0xf << 20) |
| 44 | #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_IDLE (0 << 20) |
| 45 | #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SYNC (1 << 20) |
| 46 | #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_START1 (2 << 20) |
| 47 | #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_COMMAND (3 << 20) |
| 48 | #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_ADDRESS (4 << 20) |
| 49 | #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_LENGTH (5 << 20) |
| 50 | #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_WRITE1 (6 << 20) |
| 51 | #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_READ1 (7 << 20) |
| 52 | #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_GET_M (8 << 20) |
| 53 | #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP1 (9 << 20) |
| 54 | #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP2 (10 << 20) |
| 55 | #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_REPLY (11 << 20) |
| 56 | #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_CLEANUP (12 << 20) |
| 57 | #define DPAUX_DP_AUXSTAT_REPLYTYPE_SHIFT (16) |
| 58 | #define DPAUX_DP_AUXSTAT_REPLYTYPE_MASK (0xf << 16) |
| 59 | #define DPAUX_DP_AUXSTAT_REPLYTYPE_ACK (0 << 16) |
| 60 | #define DPAUX_DP_AUXSTAT_REPLYTYPE_NACK (1 << 16) |
| 61 | #define DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER (2 << 16) |
| 62 | #define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK (4 << 16) |
| 63 | #define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER (8 << 16) |
| 64 | #define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_SHIFT (11) |
| 65 | #define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_NOT_PENDING (0 << 11) |
| 66 | #define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING (1 << 11) |
| 67 | #define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_SHIFT (10) |
| 68 | #define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_NOT_PENDING (0 << 10) |
| 69 | #define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING (1 << 10) |
| 70 | #define DPAUX_DP_AUXSTAT_RX_ERROR_SHIFT (9) |
| 71 | #define DPAUX_DP_AUXSTAT_RX_ERROR_NOT_PENDING (0 << 9) |
| 72 | #define DPAUX_DP_AUXSTAT_RX_ERROR_PENDING (1 << 9) |
| 73 | #define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_SHIFT (8) |
| 74 | #define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_NOT_PENDING (0 << 8) |
| 75 | #define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING (1 << 8) |
| 76 | #define DPAUX_DP_AUXSTAT_REPLY_M_SHIFT (0) |
| 77 | #define DPAUX_DP_AUXSTAT_REPLY_M_MASK (0xff << 0) |
| 78 | #define DPAUX_HPD_CONFIG (0x3d) |
| 79 | #define DPAUX_HPD_IRQ_CONFIG (0x41) |
| 80 | #define DPAUX_DP_AUX_CONFIG (0x45) |
| 81 | #define DPAUX_HYBRID_PADCTL (0x49) |
| 82 | #define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_SHIFT (15) |
| 83 | #define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_DISABLE (0 << 15) |
| 84 | #define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_ENABLE (1 << 15) |
| 85 | #define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_SHIFT (14) |
| 86 | #define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_DISABLE (0 << 14) |
| 87 | #define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_ENABLE (1 << 14) |
| 88 | #define DPAUX_HYBRID_PADCTL_AUX_CMH_SHIFT (12) |
| 89 | #define DPAUX_HYBRID_PADCTL_AUX_CMH_DEFAULT_MASK (0x3 << 12) |
| 90 | #define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_60 (0 << 12) |
| 91 | #define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_64 (1 << 12) |
| 92 | #define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 (2 << 12) |
| 93 | #define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_56 (3 << 12) |
| 94 | #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_SHIFT (8) |
| 95 | #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_DEFAULT_MASK (0x7 << 8) |
| 96 | #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_78 (0 << 8) |
| 97 | #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_60 (1 << 8) |
| 98 | #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_54 (2 << 8) |
| 99 | #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_45 (3 << 8) |
| 100 | #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 (4 << 8) |
| 101 | #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_42 (5 << 8) |
| 102 | #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_39 (6 << 8) |
| 103 | #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_34 (7 << 8) |
| 104 | #define DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT (2) |
| 105 | #define DPAUX_HYBRID_PADCTL_AUX_DRVI_DEFAULT_MASK (0x3f << 2) |
| 106 | #define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_SHIFT (1) |
| 107 | #define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_DISABLE (0 << 1) |
| 108 | #define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE (1 << 1) |
| 109 | #define DPAUX_HYBRID_PADCTL_MODE_SHIFT (0) |
| 110 | #define DPAUX_HYBRID_PADCTL_MODE_AUX (0) |
| 111 | #define DPAUX_HYBRID_PADCTL_MODE_I2C (1) |
| 112 | #define DPAUX_HYBRID_SPARE (0x4d) |
| 113 | #define DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP (0) |
| 114 | #define DPAUX_HYBRID_SPARE_PAD_PWR_POWERDOWN (1) |
| 115 | |
Jimmy Zhang | bd5925a | 2014-03-10 12:42:05 -0700 | [diff] [blame] | 116 | #define DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME_SHIFT (16) |
| 117 | |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 118 | /* TODO: figure out which of the NV_ constants are the same as all the other |
| 119 | * display port standard constants. |
| 120 | */ |
| 121 | |
| 122 | #define DP_AUX_DEFER_MAX_TRIES 7 |
| 123 | #define DP_AUX_TIMEOUT_MAX_TRIES 2 |
| 124 | #define DP_POWER_ON_MAX_TRIES 3 |
| 125 | #define DP_CLOCK_RECOVERY_MAX_TRIES 7 |
| 126 | #define DP_CLOCK_RECOVERY_TOT_TRIES 15 |
| 127 | |
| 128 | #define DP_AUX_MAX_BYTES 16 |
| 129 | |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 130 | #define DP_AUX_TIMEOUT_MS 40 |
| 131 | #define DP_DPCP_RETRY_SLEEP_NS 400 |
| 132 | |
Neil Chen | 8c440a6 | 2014-09-23 17:41:59 +0800 | [diff] [blame] | 133 | static const u32 tegra_dp_vs_regs[][4][4] = { |
| 134 | /* postcursor2 L0 */ |
| 135 | { |
| 136 | /* pre-emphasis: L0, L1, L2, L3 */ |
| 137 | {0x13, 0x19, 0x1e, 0x28}, /* voltage swing: L0 */ |
| 138 | {0x1e, 0x25, 0x2d}, /* L1 */ |
| 139 | {0x28, 0x32}, /* L2 */ |
| 140 | {0x3c}, /* L3 */ |
| 141 | }, |
| 142 | |
| 143 | /* postcursor2 L1 */ |
| 144 | { |
| 145 | {0x12, 0x17, 0x1b, 0x25}, |
| 146 | {0x1c, 0x23, 0x2a}, |
| 147 | {0x25, 0x2f}, |
| 148 | {0x39}, |
| 149 | }, |
| 150 | |
| 151 | /* postcursor2 L2 */ |
| 152 | { |
| 153 | {0x12, 0x16, 0x1a, 0x22}, |
| 154 | {0x1b, 0x20, 0x27}, |
| 155 | {0x24, 0x2d}, |
| 156 | {0x36}, |
| 157 | }, |
| 158 | |
| 159 | /* postcursor2 L3 */ |
| 160 | { |
| 161 | {0x11, 0x14, 0x17, 0x1f}, |
| 162 | {0x19, 0x1e, 0x24}, |
| 163 | {0x22, 0x2a}, |
| 164 | {0x32}, |
| 165 | }, |
| 166 | }; |
| 167 | |
| 168 | static const u32 tegra_dp_pe_regs[][4][4] = { |
| 169 | /* postcursor2 L0 */ |
| 170 | { |
| 171 | /* pre-emphasis: L0, L1, L2, L3 */ |
| 172 | {0x00, 0x09, 0x13, 0x25}, /* voltage swing: L0 */ |
| 173 | {0x00, 0x0f, 0x1e}, /* L1 */ |
| 174 | {0x00, 0x14}, /* L2 */ |
| 175 | {0x00}, /* L3 */ |
| 176 | }, |
| 177 | |
| 178 | /* postcursor2 L1 */ |
| 179 | { |
| 180 | {0x00, 0x0a, 0x14, 0x28}, |
| 181 | {0x00, 0x0f, 0x1e}, |
| 182 | {0x00, 0x14}, |
| 183 | {0x00}, |
| 184 | }, |
| 185 | |
| 186 | /* postcursor2 L2 */ |
| 187 | { |
| 188 | {0x00, 0x0a, 0x14, 0x28}, |
| 189 | {0x00, 0x0f, 0x1e}, |
| 190 | {0x00, 0x14}, |
| 191 | {0x00}, |
| 192 | }, |
| 193 | |
| 194 | /* postcursor2 L3 */ |
| 195 | { |
| 196 | {0x00, 0x0a, 0x14, 0x28}, |
| 197 | {0x00, 0x0f, 0x1e}, |
| 198 | {0x00, 0x14}, |
| 199 | {0x00}, |
| 200 | }, |
| 201 | }; |
| 202 | |
| 203 | static const u32 tegra_dp_pc_regs[][4][4] = { |
| 204 | /* postcursor2 L0 */ |
| 205 | { |
| 206 | /* pre-emphasis: L0, L1, L2, L3 */ |
| 207 | {0x00, 0x00, 0x00, 0x00}, /* voltage swing: L0 */ |
| 208 | {0x00, 0x00, 0x00}, /* L1 */ |
| 209 | {0x00, 0x00}, /* L2 */ |
| 210 | {0x00}, /* L3 */ |
| 211 | }, |
| 212 | |
| 213 | /* postcursor2 L1 */ |
| 214 | { |
| 215 | {0x02, 0x02, 0x04, 0x05}, |
| 216 | {0x02, 0x04, 0x05}, |
| 217 | {0x04, 0x05}, |
| 218 | {0x05}, |
| 219 | }, |
| 220 | |
| 221 | /* postcursor2 L2 */ |
| 222 | { |
| 223 | {0x04, 0x05, 0x08, 0x0b}, |
| 224 | {0x05, 0x09, 0x0b}, |
| 225 | {0x08, 0x0a}, |
| 226 | {0x0b}, |
| 227 | }, |
| 228 | |
| 229 | /* postcursor2 L3 */ |
| 230 | { |
| 231 | {0x05, 0x09, 0x0b, 0x12}, |
| 232 | {0x09, 0x0d, 0x12}, |
| 233 | {0x0b, 0x0f}, |
| 234 | {0x12}, |
| 235 | }, |
| 236 | }; |
| 237 | |
| 238 | static const u32 tegra_dp_tx_pu[][4][4] = { |
| 239 | /* postcursor2 L0 */ |
| 240 | { |
| 241 | /* pre-emphasis: L0, L1, L2, L3 */ |
| 242 | {0x20, 0x30, 0x40, 0x60}, /* voltage swing: L0 */ |
| 243 | {0x30, 0x40, 0x60}, /* L1 */ |
| 244 | {0x40, 0x60}, /* L2 */ |
| 245 | {0x60}, /* L3 */ |
| 246 | }, |
| 247 | |
| 248 | /* postcursor2 L1 */ |
| 249 | { |
| 250 | {0x20, 0x20, 0x30, 0x50}, |
| 251 | {0x30, 0x40, 0x50}, |
| 252 | {0x40, 0x50}, |
| 253 | {0x60}, |
| 254 | }, |
| 255 | |
| 256 | /* postcursor2 L2 */ |
| 257 | { |
| 258 | {0x20, 0x20, 0x30, 0x40}, |
| 259 | {0x30, 0x30, 0x40}, |
| 260 | {0x40, 0x50}, |
| 261 | {0x60}, |
| 262 | }, |
| 263 | |
| 264 | /* postcursor2 L3 */ |
| 265 | { |
| 266 | {0x20, 0x20, 0x20, 0x40}, |
| 267 | {0x30, 0x30, 0x40}, |
| 268 | {0x40, 0x40}, |
| 269 | {0x60}, |
| 270 | }, |
| 271 | }; |
| 272 | |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 273 | enum { |
| 274 | driveCurrent_Level0 = 0, |
| 275 | driveCurrent_Level1 = 1, |
| 276 | driveCurrent_Level2 = 2, |
| 277 | driveCurrent_Level3 = 3, |
| 278 | }; |
| 279 | |
| 280 | enum { |
| 281 | preEmphasis_Disabled = 0, |
| 282 | preEmphasis_Level1 = 1, |
| 283 | preEmphasis_Level2 = 2, |
| 284 | preEmphasis_Level3 = 3, |
| 285 | }; |
| 286 | |
| 287 | enum { |
| 288 | postCursor2_Level0 = 0, |
| 289 | postCursor2_Level1 = 1, |
| 290 | postCursor2_Level2 = 2, |
| 291 | postCursor2_Level3 = 3, |
| 292 | postCursor2_Supported |
| 293 | }; |
| 294 | |
Neil Chen | 8c440a6 | 2014-09-23 17:41:59 +0800 | [diff] [blame] | 295 | static inline int tegra_dp_is_max_vs(u32 pe, u32 vs) |
| 296 | { |
| 297 | return (vs < (driveCurrent_Level3 - pe)) ? 0 : 1; |
| 298 | } |
| 299 | |
| 300 | static inline int tegra_dp_is_max_pe(u32 pe, u32 vs) |
| 301 | { |
| 302 | return (pe < (preEmphasis_Level3 - vs)) ? 0 : 1; |
| 303 | } |
| 304 | |
| 305 | static inline int tegra_dp_is_max_pc(u32 pc) |
| 306 | { |
| 307 | return (pc < postCursor2_Level3) ? 0 : 1; |
| 308 | } |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 309 | |
| 310 | /* the +10ms is the time for power rail going up from 10-90% or |
| 311 | 90%-10% on powerdown */ |
| 312 | /* Time from power-rail is turned on and aux/12c-over-aux is available */ |
| 313 | #define EDP_PWR_ON_TO_AUX_TIME_MS (200+10) |
| 314 | /* Time from power-rail is turned on and MainLink is available for LT */ |
| 315 | #define EDP_PWR_ON_TO_ML_TIME_MS (200+10) |
| 316 | /* Time from turning off power to turn-it on again (does not include post |
| 317 | poweron time) */ |
| 318 | #define EDP_PWR_OFF_TO_ON_TIME_MS (500+10) |
| 319 | |
| 320 | struct tegra_dc_dp_data { |
Jimmy Zhang | bd5925a | 2014-03-10 12:42:05 -0700 | [diff] [blame] | 321 | struct tegra_dc *dc; |
Julius Werner | edf6b57 | 2013-10-25 17:49:26 -0700 | [diff] [blame] | 322 | struct tegra_dc_sor_data sor; |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 323 | void *aux_base; |
Jimmy Zhang | bd5925a | 2014-03-10 12:42:05 -0700 | [diff] [blame] | 324 | struct tegra_dc_dp_link_config link_cfg; |
| 325 | u8 revision; |
| 326 | int enabled; |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 327 | }; |
| 328 | |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 329 | /* DPCD definitions */ |
| 330 | /* you know, all the vendors pick their own set of defines. |
| 331 | * All of them. |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 332 | */ |
| 333 | #define NV_DPCD_REV (0x00000000) |
| 334 | #define NV_DPCD_REV_MAJOR_SHIFT (4) |
| 335 | #define NV_DPCD_REV_MAJOR_MASK (0xf << 4) |
| 336 | #define NV_DPCD_REV_MINOR_SHIFT (0) |
| 337 | #define NV_DPCD_REV_MINOR_MASK (0xf) |
| 338 | #define NV_DPCD_MAX_LINK_BANDWIDTH (0x00000001) |
| 339 | #define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_1_62_GPBS (0x00000006) |
| 340 | #define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_2_70_GPBS (0x0000000a) |
| 341 | #define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_5_40_GPBS (0x00000014) |
| 342 | #define NV_DPCD_MAX_LANE_COUNT (0x00000002) |
| 343 | #define NV_DPCD_MAX_LANE_COUNT_MASK (0x1f) |
| 344 | #define NV_DPCD_MAX_LANE_COUNT_LANE_1 (0x00000001) |
| 345 | #define NV_DPCD_MAX_LANE_COUNT_LANE_2 (0x00000002) |
| 346 | #define NV_DPCD_MAX_LANE_COUNT_LANE_4 (0x00000004) |
Neil Chen | 8c440a6 | 2014-09-23 17:41:59 +0800 | [diff] [blame] | 347 | #define NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_YES (0x00000001 << 6) |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 348 | #define NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_NO (0x00000000 << 7) |
| 349 | #define NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES (0x00000001 << 7) |
| 350 | #define NV_DPCD_MAX_DOWNSPREAD (0x00000003) |
| 351 | #define NV_DPCD_MAX_DOWNSPREAD_VAL_NONE (0x00000000) |
| 352 | #define NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT (0x00000001) |
| 353 | #define NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_F (0x00000000 << 6) |
| 354 | #define NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T (0x00000001 << 6) |
| 355 | #define NV_DPCD_EDP_CONFIG_CAP (0x0000000D) |
| 356 | #define NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_NO (0x00000000) |
| 357 | #define NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES (0x00000001) |
| 358 | #define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_NO (0x00000000 << 1) |
| 359 | #define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES (0x00000001 << 1) |
Neil Chen | 8c440a6 | 2014-09-23 17:41:59 +0800 | [diff] [blame] | 360 | #define NV_DPCD_TRAINING_AUX_RD_INTERVAL (0x0000000E) |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 361 | #define NV_DPCD_LINK_BANDWIDTH_SET (0x00000100) |
| 362 | #define NV_DPCD_LANE_COUNT_SET (0x00000101) |
| 363 | #define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_F (0x00000000 << 7) |
| 364 | #define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T (0x00000001 << 7) |
| 365 | #define NV_DPCD_TRAINING_PATTERN_SET (0x00000102) |
| 366 | #define NV_DPCD_TRAINING_PATTERN_SET_TPS_MASK 0x3 |
| 367 | #define NV_DPCD_TRAINING_PATTERN_SET_TPS_NONE (0x00000000) |
| 368 | #define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP1 (0x00000001) |
| 369 | #define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP2 (0x00000002) |
| 370 | #define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP3 (0x00000003) |
| 371 | #define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F (0x00000000 << 5) |
| 372 | #define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T (0x00000001 << 5) |
| 373 | #define NV_DPCD_TRAINING_LANE0_SET (0x00000103) |
| 374 | #define NV_DPCD_TRAINING_LANE1_SET (0x00000104) |
| 375 | #define NV_DPCD_TRAINING_LANE2_SET (0x00000105) |
| 376 | #define NV_DPCD_TRAINING_LANE3_SET (0x00000106) |
| 377 | #define NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT 0 |
| 378 | #define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T (0x00000001 << 2) |
Neil Chen | 8c440a6 | 2014-09-23 17:41:59 +0800 | [diff] [blame] | 379 | #define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F (0x00000000 << 2) |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 380 | #define NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3 |
| 381 | #define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T (0x00000001 << 5) |
Neil Chen | 8c440a6 | 2014-09-23 17:41:59 +0800 | [diff] [blame] | 382 | #define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F (0x00000000 << 5) |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 383 | #define NV_DPCD_DOWNSPREAD_CTRL (0x00000107) |
| 384 | #define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_NONE (0x00000000 << 4) |
| 385 | #define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_LT_0_5 (0x00000001 << 4) |
| 386 | #define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET (0x00000108) |
| 387 | #define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B10B 1 |
| 388 | #define NV_DPCD_EDP_CONFIG_SET (0x0000010A) |
| 389 | #define NV_DPCD_EDP_CONFIG_SET_ASC_RESET_DISABLE (0x00000000) |
| 390 | #define NV_DPCD_EDP_CONFIG_SET_ASC_RESET_ENABLE (0x00000001) |
| 391 | #define NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_DISABLE (0x00000000 << 1) |
| 392 | #define NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_ENABLE (0x00000001 << 1) |
| 393 | #define NV_DPCD_TRAINING_LANE0_1_SET2 (0x0000010F) |
| 394 | #define NV_DPCD_TRAINING_LANE2_3_SET2 (0x00000110) |
| 395 | #define NV_DPCD_LANEX_SET2_PC2_SHIFT 0 |
| 396 | #define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T (0x00000001 << 2) |
Neil Chen | 8c440a6 | 2014-09-23 17:41:59 +0800 | [diff] [blame] | 397 | #define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_F (0x00000000 << 2) |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 398 | #define NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT 4 |
| 399 | #define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T (0x00000001 << 6) |
Neil Chen | 8c440a6 | 2014-09-23 17:41:59 +0800 | [diff] [blame] | 400 | #define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_F (0x00000000 << 6) |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 401 | #define NV_DPCD_SINK_COUNT (0x00000200) |
| 402 | #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR (0x00000201) |
| 403 | #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_NO (0x00000000 << 1) |
| 404 | #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_YES (0x00000001 << 1) |
| 405 | #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_NO (0x00000000 << 2) |
| 406 | #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_YES (0x00000001 << 2) |
| 407 | #define NV_DPCD_LANE0_1_STATUS (0x00000202) |
| 408 | #define NV_DPCD_LANE2_3_STATUS (0x00000203) |
| 409 | #define NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT 0 |
| 410 | #define NV_DPCD_STATUS_LANEX_CR_DONE_NO (0x00000000) |
| 411 | #define NV_DPCD_STATUS_LANEX_CR_DONE_YES (0x00000001) |
| 412 | #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT 1 |
| 413 | #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO (0x00000000 << 1) |
| 414 | #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES (0x00000001 << 1) |
| 415 | #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT 2 |
| 416 | #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO (0x00000000 << 2) |
| 417 | #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES (0x00000001 << 2) |
| 418 | #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT 4 |
| 419 | #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO (0x00000000 << 4) |
| 420 | #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES (0x00000001 << 4) |
| 421 | #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT 5 |
| 422 | #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000 << 5) |
| 423 | #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001 << 5) |
| 424 | #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT 6 |
| 425 | #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO (0x00000000 << 6) |
| 426 | #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES (0x00000001 << 6) |
| 427 | #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED (0x00000204) |
| 428 | #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_NO (0x00000000) |
| 429 | #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES (0x00000001) |
Jimmy Zhang | fff922b | 2015-01-06 15:08:54 -0800 | [diff] [blame] | 430 | #define NV_DPCD_SINK_STATUS (0x00000205) |
| 431 | #define NV_DPCD_SINK_STATUS_PORT0_IN_SYNC (0x1 << 0) |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 432 | #define NV_DPCD_LANE0_1_ADJUST_REQ (0x00000206) |
| 433 | #define NV_DPCD_LANE2_3_ADJUST_REQ (0x00000207) |
| 434 | #define NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT 0 |
| 435 | #define NV_DPCD_ADJUST_REQ_LANEX_DC_MASK 0x3 |
| 436 | #define NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT 2 |
| 437 | #define NV_DPCD_ADJUST_REQ_LANEX_PE_MASK (0x3 << 2) |
| 438 | #define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT 4 |
| 439 | #define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK (0x3 << 4) |
| 440 | #define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT 6 |
| 441 | #define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK (0x3 << 6) |
| 442 | #define NV_DPCD_ADJUST_REQ_POST_CURSOR2 (0x0000020C) |
| 443 | #define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK 0x3 |
| 444 | #define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(i) (i*2) |
| 445 | #define NV_DPCD_TEST_REQUEST (0x00000218) |
| 446 | #define NV_DPCD_SOURCE_IEEE_OUI (0x00000300) |
| 447 | #define NV_DPCD_SINK_IEEE_OUI (0x00000400) |
| 448 | #define NV_DPCD_BRANCH_IEEE_OUI (0x00000500) |
| 449 | #define NV_DPCD_SET_POWER (0x00000600) |
| 450 | #define NV_DPCD_SET_POWER_VAL_RESERVED (0x00000000) |
| 451 | #define NV_DPCD_SET_POWER_VAL_D0_NORMAL (0x00000001) |
| 452 | #define NV_DPCD_SET_POWER_VAL_D3_PWRDWN (0x00000002) |
| 453 | #define NV_DPCD_HDCP_BKSV_OFFSET (0x00068000) |
| 454 | #define NV_DPCD_HDCP_RPRIME_OFFSET (0x00068005) |
| 455 | #define NV_DPCD_HDCP_AKSV_OFFSET (0x00068007) |
| 456 | #define NV_DPCD_HDCP_AN_OFFSET (0x0006800C) |
| 457 | #define NV_DPCD_HDCP_VPRIME_OFFSET (0x00068014) |
| 458 | #define NV_DPCD_HDCP_BCAPS_OFFSET (0x00068028) |
| 459 | #define NV_DPCD_HDCP_BSTATUS_OFFSET (0x00068029) |
| 460 | #define NV_DPCD_HDCP_BINFO_OFFSET (0x0006802A) |
| 461 | #define NV_DPCD_HDCP_KSV_FIFO_OFFSET (0x0006802C) |
| 462 | #define NV_DPCD_HDCP_AINFO_OFFSET (0x0006803B) |
Hung-Te Lin | 2fc3b62 | 2013-10-21 21:43:03 +0800 | [diff] [blame] | 463 | #endif /* __SOC_NVIDIA_TEGRA_DISPLAYPORT_H__ */ |