Angel Pons | a2ee761 | 2020-04-04 18:51:15 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Jimmy Zhang | bf04eda | 2014-02-11 17:21:20 -0800 | [diff] [blame] | 2 | |
| 3 | #ifndef __SOC_NVIDIA_TEGRA_APBMISC_H__ |
| 4 | #define __SOC_NVIDIA_TEGRA_APBMISC_H__ |
| 5 | |
| 6 | #include <stdint.h> |
| 7 | |
| 8 | struct apbmisc { |
Tom Warren | 355dc1e | 2015-05-21 15:21:12 -0700 | [diff] [blame] | 9 | u32 reserved0[2]; /* ABP_MISC_PP_ offsets 00 and 04 */ |
| 10 | u32 pp_strapping_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */ |
| 11 | u32 reserved1[6]; /* ABP_MISC_PP_ offsets 0C-20 */ |
Jimmy Zhang | bf04eda | 2014-02-11 17:21:20 -0800 | [diff] [blame] | 12 | u32 pp_config_ctl; /* _CONFIG_CTL_0, offset 24 */ |
Tom Warren | 355dc1e | 2015-05-21 15:21:12 -0700 | [diff] [blame] | 13 | u32 reserved2[6]; /* APB_MISC_PP_ offsets 28-3C */ |
Ken Chang | 41359bd | 2014-04-21 17:54:28 +0800 | [diff] [blame] | 14 | u32 pp_pinmux_global; /* _PINMUX_GLOBAL_0, offset 40 */ |
Jimmy Zhang | bf04eda | 2014-02-11 17:21:20 -0800 | [diff] [blame] | 15 | }; |
| 16 | |
| 17 | #define PP_CONFIG_CTL_TBE (1 << 7) |
| 18 | #define PP_CONFIG_CTL_JTAG (1 << 6) |
| 19 | |
Ken Chang | 41359bd | 2014-04-21 17:54:28 +0800 | [diff] [blame] | 20 | #define PP_PINMUX_CLAMP_INPUTS (1 << 0) |
| 21 | |
Aaron Durbin | bf53418 | 2014-08-04 11:40:45 -0500 | [diff] [blame] | 22 | enum { |
| 23 | MISC_GP_HIDREV = 0x804 |
| 24 | }; |
| 25 | |
| 26 | struct tegra_revision { |
| 27 | int hid_fam; |
| 28 | int chip_id; |
| 29 | int major; |
| 30 | int minor; |
| 31 | }; |
Ken Chang | 41359bd | 2014-04-21 17:54:28 +0800 | [diff] [blame] | 32 | |
Jimmy Zhang | bf04eda | 2014-02-11 17:21:20 -0800 | [diff] [blame] | 33 | void enable_jtag(void); |
Ken Chang | 41359bd | 2014-04-21 17:54:28 +0800 | [diff] [blame] | 34 | void clamp_tristate_inputs(void); |
Aaron Durbin | bf53418 | 2014-08-04 11:40:45 -0500 | [diff] [blame] | 35 | void tegra_revision_info(struct tegra_revision *id); |
Jimmy Zhang | bf04eda | 2014-02-11 17:21:20 -0800 | [diff] [blame] | 36 | |
Tom Warren | 355dc1e | 2015-05-21 15:21:12 -0700 | [diff] [blame] | 37 | enum { |
| 38 | PP_STRAPPING_OPT_A_RAM_CODE_SHIFT = 4, |
| 39 | PP_STRAPPING_OPT_A_RAM_CODE_MASK = |
| 40 | 0xF << PP_STRAPPING_OPT_A_RAM_CODE_SHIFT, |
| 41 | }; |
| 42 | |
Jimmy Zhang | bf04eda | 2014-02-11 17:21:20 -0800 | [diff] [blame] | 43 | #endif /* __SOC_NVIDIA_TEGRA_APBMISC_H__ */ |