Angel Pons | 6ad9176 | 2020-04-03 01:23:24 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 2 | |
| 3 | #include <arch/io.h> |
| 4 | #include <bootstate.h> |
| 5 | #include <cf9_reset.h> |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 6 | #include <device/pci_def.h> |
| 7 | #include <device/pci_ids.h> |
| 8 | #include <device/pci_ops.h> |
| 9 | #include <gpio.h> |
| 10 | #include <hwilib.h> |
| 11 | #include <intelblocks/lpc_lib.h> |
| 12 | #include <intelblocks/pcr.h> |
| 13 | #include <soc/pcr_ids.h> |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 14 | #include <baseboard/variants.h> |
| 15 | #include <types.h> |
| 16 | |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 17 | void variant_mainboard_final(void) |
| 18 | { |
| 19 | struct device *dev = NULL; |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 20 | |
| 21 | /* PIR6 register mapping for PCIe root ports |
Mario Scheithauer | 08706a3 | 2023-05-09 13:34:05 +0200 | [diff] [blame] | 22 | INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC# */ |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 23 | pcr_write16(PID_ITSS, 0x314c, 0x2103); |
| 24 | |
| 25 | /* Enable CLKRUN_EN for power gating LPC */ |
| 26 | lpc_enable_pci_clk_cntl(); |
| 27 | |
| 28 | /* |
Mario Scheithauer | 08706a3 | 2023-05-09 13:34:05 +0200 | [diff] [blame] | 29 | * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2 offset 0x341D |
| 30 | * bit3 and bit0. |
| 31 | * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2 offset 0x341C bit |
| 32 | * [3:0]. |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 33 | */ |
| 34 | pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN)); |
| 35 | |
Werner Zeh | 1412ffa | 2021-07-20 07:33:20 +0200 | [diff] [blame] | 36 | /* Set Master Enable for on-board PCI device if allowed. */ |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 37 | dev = dev_find_device(PCI_VID_SIEMENS, 0x403e, 0); |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 38 | if (dev) { |
Werner Zeh | e8fc8f3 | 2021-07-22 06:44:01 +0200 | [diff] [blame] | 39 | if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) |
Werner Zeh | 1412ffa | 2021-07-20 07:33:20 +0200 | [diff] [blame] | 40 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 41 | |
Mario Scheithauer | 08706a3 | 2023-05-09 13:34:05 +0200 | [diff] [blame] | 42 | /* Disable clock outputs 0-3 (CLKOUT) for upstream XIO2001 PCIe to PCI |
| 43 | Bridge. */ |
Arthur Heymans | 7fcd4d5 | 2023-08-24 15:12:19 +0200 | [diff] [blame] | 44 | struct device *parent = dev->upstream->dev; |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 45 | if (parent && parent->device == PCI_DID_TI_XIO2001) |
Werner Zeh | 4f7fe49 | 2019-11-08 09:50:20 +0100 | [diff] [blame] | 46 | pci_write_config8(parent, 0xd8, 0x0F); |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 47 | } |
| 48 | |
Mario Scheithauer | 08706a3 | 2023-05-09 13:34:05 +0200 | [diff] [blame] | 49 | /* Disable clock outputs 2-5 (CLKOUT) for another XIO2001 PCIe to PCI Bridge on this |
| 50 | mainboard. */ |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 51 | dev = dev_find_device(PCI_VID_SIEMENS, 0x403f, 0); |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 52 | if (dev) { |
Arthur Heymans | 7fcd4d5 | 2023-08-24 15:12:19 +0200 | [diff] [blame] | 53 | struct device *parent = dev->upstream->dev; |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 54 | if (parent && parent->device == PCI_DID_TI_XIO2001) |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 55 | pci_write_config8(parent, 0xd8, 0x3c); |
| 56 | } |
| 57 | |
Mario Scheithauer | 08706a3 | 2023-05-09 13:34:05 +0200 | [diff] [blame] | 58 | /* Set Full Reset Bit in Reset Control Register (I/O port CF9h). When Bit 3 is set to 1 |
| 59 | and then the reset button is pressed the PCH will drive SLP_S3 active (low). SLP_S3 |
| 60 | is then used on the mainboard to generate the right reset timing. */ |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 61 | outb(FULL_RST, RST_CNT); |
| 62 | } |
| 63 | |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 64 | static void finalize_boot(void *unused) |
| 65 | { |
| 66 | /* Set coreboot ready LED. */ |
| 67 | gpio_output(CNV_RGI_DT, 1); |
| 68 | } |
| 69 | |
Werner Zeh | 0dc87ef | 2019-10-22 15:08:19 +0200 | [diff] [blame] | 70 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); |