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review.coreboot.org / coreboot / 31402178c56108e752b95c34562b6e3554a2c1d8 / . / src / mainboard / intel / tglrvp / dsdt.asl
blob: 7ccd5693257c0e48e32bdacae77597ff6b90eeb2 [file] [log] [blame]
Angel Pons60ec3652020-04-03 01:22:13 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Ravi Sarawadiebb2d3c2019-12-19 23:01:48 -0800[diff] [blame]2
Furquan Shaikh76cedd22020-05-02 10:24:23 -0700[diff] [blame]3#include <acpi/acpi.h>
Ravi Sarawadiebb2d3c2019-12-19 23:01:48 -0800[diff] [blame]4#include <baseboard/ec.h>
5#include <baseboard/gpio.h>
6
7DefinitionBlock(
8 "dsdt.aml",
9 "DSDT",
Elyes HAOUAS90d00de2020-10-05 16:38:53 +0200[diff] [blame]10 ACPI_DSDT_REV_2,
Ravi Sarawadiebb2d3c2019-12-19 23:01:48 -0800[diff] [blame]11 OEM_ID,
12 ACPI_TABLE_CREATOR,
Angel Pons621aff92022-08-14 12:35:22 +0200[diff] [blame]13 0x20110725
Ravi Sarawadiebb2d3c2019-12-19 23:01:48 -0800[diff] [blame]14)
15{
Kyösti Mälkkicf246d52021-01-21 08:17:00 +0200[diff] [blame]16 #include <acpi/dsdt_top.asl>
Subrata Banik6577ec42020-10-03 23:07:36 +0530[diff] [blame]17 #include <soc/intel/common/block/acpi/acpi/platform.asl>
Ravi Sarawadiebb2d3c2019-12-19 23:01:48 -0800[diff] [blame]18 #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
Ravi Sarawadiebb2d3c2019-12-19 23:01:48 -0800[diff] [blame]19 #include <cpu/intel/common/acpi/cpu.asl>
20
21 Scope (\_SB) {
22 Device (PCI0)
23 {
24 #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
25 #include <soc/intel/tigerlake/acpi/southbridge.asl>
John Zhao4e300cc2020-04-22 09:23:48 -0700[diff] [blame]26 #include <soc/intel/tigerlake/acpi/tcss.asl>
Subrata Banik73968fd2020-10-03 21:04:04 +0530[diff] [blame]27 #include <soc/intel/common/block/acpi/acpi/ipu.asl>
Ravi Sarawadiebb2d3c2019-12-19 23:01:48 -0800[diff] [blame]28 }
29 }
30
Ravi Sarawadiebb2d3c2019-12-19 23:01:48 -0800[diff] [blame]31#if CONFIG(EC_GOOGLE_CHROMEEC)
Jon Murphyc4e90452022-06-28 10:36:23 -0600[diff] [blame]32 /* ChromeOS Embedded Controller */
Ravi Sarawadiebb2d3c2019-12-19 23:01:48 -0800[diff] [blame]33 Scope (\_SB.PCI0.LPCB)
34 {
35 /* ACPI code for EC SuperIO functions */
36 #include <ec/google/chromeec/acpi/superio.asl>
37 /* ACPI code for EC functions */
38 #include <ec/google/chromeec/acpi/ec.asl>
39 }
40#endif
41
Ravi Sarawadiebb2d3c2019-12-19 23:01:48 -0800[diff] [blame]42 #include <southbridge/intel/common/acpi/sleepstates.asl>
43
Wonkyu Kimf93c1572019-12-19 19:27:34 -0800[diff] [blame]44 /* Camera */
Wonkyu Kimf93c1572019-12-19 19:27:34 -0800[diff] [blame]45 #include "acpi/mipi_camera.asl"
Ravi Sarawadiebb2d3c2019-12-19 23:01:48 -0800[diff] [blame]46}