Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 3 | /* TODO: Update for Phoenix */ |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 4 | |
| 5 | #include <acpi/acpigen.h> |
| 6 | #include <amdblocks/acpi.h> |
| 7 | #include <amdblocks/alib.h> |
Arthur Heymans | ce17972 | 2023-06-07 15:27:18 +0200 | [diff] [blame] | 8 | #include <amdblocks/data_fabric.h> |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 9 | #include <amdblocks/ioapic.h> |
Felix Held | 12a4482 | 2023-06-02 15:30:50 +0200 | [diff] [blame] | 10 | #include <amdblocks/iomap.h> |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 11 | #include <amdblocks/memmap.h> |
Felix Held | e0850ad | 2023-07-18 20:37:50 +0200 | [diff] [blame] | 12 | #include <amdblocks/root_complex.h> |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 13 | #include <arch/ioapic.h> |
Felix Held | a4ced63 | 2023-06-05 21:22:15 +0200 | [diff] [blame] | 14 | #include <arch/vga.h> |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 15 | #include <cbmem.h> |
| 16 | #include <console/console.h> |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 17 | #include <device/device.h> |
| 18 | #include <device/pci.h> |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 19 | #include <soc/iomap.h> |
| 20 | #include <stdint.h> |
| 21 | #include "chip.h" |
| 22 | |
| 23 | #define DPTC_TOTAL_UPDATE_PARAMS 7 |
| 24 | |
| 25 | struct dptc_input { |
| 26 | uint16_t size; |
| 27 | struct alib_dptc_param params[DPTC_TOTAL_UPDATE_PARAMS]; |
| 28 | } __packed; |
| 29 | |
| 30 | #define DPTC_INPUTS(_thermctllmit, _sustained, _fast, _slow, \ |
| 31 | _vrmCurrentLimit, _vrmMaxCurrentLimit, _vrmSocCurrentLimit) \ |
| 32 | { \ |
| 33 | .size = sizeof(struct dptc_input), \ |
| 34 | .params = { \ |
| 35 | { \ |
| 36 | .id = ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID, \ |
| 37 | .value = _thermctllmit, \ |
| 38 | }, \ |
| 39 | { \ |
| 40 | .id = ALIB_DPTC_SUSTAINED_POWER_LIMIT_ID, \ |
| 41 | .value = _sustained, \ |
| 42 | }, \ |
| 43 | { \ |
| 44 | .id = ALIB_DPTC_FAST_PPT_LIMIT_ID, \ |
| 45 | .value = _fast, \ |
| 46 | }, \ |
| 47 | { \ |
| 48 | .id = ALIB_DPTC_SLOW_PPT_LIMIT_ID, \ |
| 49 | .value = _slow, \ |
| 50 | }, \ |
| 51 | { \ |
| 52 | .id = ALIB_DPTC_VRM_CURRENT_LIMIT_ID, \ |
| 53 | .value = _vrmCurrentLimit, \ |
| 54 | }, \ |
| 55 | { \ |
| 56 | .id = ALIB_DPTC_VRM_MAXIMUM_CURRENT_LIMIT, \ |
| 57 | .value = _vrmMaxCurrentLimit, \ |
| 58 | }, \ |
| 59 | { \ |
| 60 | .id = ALIB_DPTC_VRM_SOC_CURRENT_LIMIT_ID, \ |
| 61 | .value = _vrmSocCurrentLimit, \ |
| 62 | }, \ |
| 63 | }, \ |
| 64 | } |
| 65 | |
| 66 | /* |
| 67 | * |
| 68 | * +--------------------------------+ |
| 69 | * | | |
| 70 | * | | |
| 71 | * | | |
| 72 | * | | |
| 73 | * | | |
| 74 | * | | |
| 75 | * | | |
| 76 | * reserved_dram_end +--------------------------------+ |
| 77 | * | | |
| 78 | * | verstage (if reqd) | |
| 79 | * | (VERSTAGE_SIZE) | |
| 80 | * +--------------------------------+ VERSTAGE_ADDR |
| 81 | * | | |
| 82 | * | FSP-M | |
| 83 | * | (FSP_M_SIZE) | |
| 84 | * +--------------------------------+ FSP_M_ADDR |
| 85 | * | romstage | |
| 86 | * | (ROMSTAGE_SIZE) | |
| 87 | * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END |
| 88 | * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 |
| 89 | * | bootblock | |
| 90 | * | (C_ENV_BOOTBLOCK_SIZE) | |
| 91 | * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE |
| 92 | * | Unused hole | |
| 93 | * | (30KiB) | |
| 94 | * +--------------------------------+ |
| 95 | * | FMAP cache (FMAP_SIZE) | |
| 96 | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 |
| 97 | * | Early Timestamp region (512B) | |
| 98 | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE |
| 99 | * | Preram CBMEM console | |
| 100 | * | (PRERAM_CBMEM_CONSOLE_SIZE) | |
| 101 | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE |
| 102 | * | PSP shared (vboot workbuf) | |
| 103 | * | (PSP_SHAREDMEM_SIZE) | |
| 104 | * +--------------------------------+ PSP_SHAREDMEM_BASE |
| 105 | * | APOB (120KiB) | |
| 106 | * +--------------------------------+ PSP_APOB_DRAM_ADDRESS |
| 107 | * | Early BSP stack | |
| 108 | * | (EARLYRAM_BSP_STACK_SIZE) | |
| 109 | * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE |
| 110 | * | DRAM | |
| 111 | * +--------------------------------+ 0x100000 |
| 112 | * | Option ROM | |
| 113 | * +--------------------------------+ 0xc0000 |
| 114 | * | Legacy VGA | |
| 115 | * +--------------------------------+ 0xa0000 |
| 116 | * | DRAM | |
| 117 | * +--------------------------------+ 0x0 |
| 118 | */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 119 | void read_soc_memmap_resources(struct device *dev, unsigned long *idx) |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 120 | { |
| 121 | uint32_t mem_usable = (uintptr_t)cbmem_top(); |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 122 | |
| 123 | uintptr_t early_reserved_dram_start, early_reserved_dram_end; |
| 124 | const struct memmap_early_dram *e = memmap_get_early_dram_usage(); |
| 125 | |
| 126 | early_reserved_dram_start = e->base; |
| 127 | early_reserved_dram_end = e->base + e->size; |
| 128 | |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 129 | fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); |
Felix Held | d0959dc | 2023-05-10 15:07:47 +0200 | [diff] [blame] | 130 | |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 131 | /* 0x0 - 0x9ffff */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 132 | ram_range(dev, (*idx)++, 0, 0xa0000); |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 133 | |
| 134 | /* 0xa0000 - 0xbffff: legacy VGA */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 135 | mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 136 | |
| 137 | /* 0xc0000 - 0xfffff: Option ROM */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 138 | reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 139 | |
| 140 | /* 1MiB - bottom of DRAM reserved for early coreboot usage */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 141 | ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 142 | |
| 143 | /* DRAM reserved for early coreboot usage */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 144 | reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 145 | |
| 146 | /* |
| 147 | * top of DRAM consumed early - low top usable RAM |
| 148 | * cbmem_top() accounts for low UMA and TSEG if they are used. |
| 149 | */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 150 | ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 151 | |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 152 | mmconf_resource(dev, (*idx)++); |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 153 | |
Felix Held | 12a4482 | 2023-06-02 15:30:50 +0200 | [diff] [blame] | 154 | /* Reserve fixed IOMMU MMIO region */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 155 | mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); |
Felix Held | 12a4482 | 2023-06-02 15:30:50 +0200 | [diff] [blame] | 156 | |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 157 | read_fsp_resources(dev, idx); |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 158 | } |
| 159 | |
| 160 | static void root_complex_init(struct device *dev) |
| 161 | { |
Kyösti Mälkki | 2e65e9c | 2021-06-16 11:00:40 +0300 | [diff] [blame] | 162 | register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 163 | } |
| 164 | |
| 165 | static void acipgen_dptci(void) |
| 166 | { |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 167 | const struct soc_amd_phoenix_config *config = config_of_soc(); |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 168 | |
| 169 | /* Normal mode DPTC values. */ |
| 170 | struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC, |
| 171 | config->sustained_power_limit_mW, |
| 172 | config->fast_ppt_limit_mW, |
| 173 | config->slow_ppt_limit_mW, |
| 174 | config->vrm_current_limit_mA, |
| 175 | config->vrm_maximum_current_limit_mA, |
| 176 | config->vrm_soc_current_limit_mA); |
| 177 | acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input)); |
| 178 | |
| 179 | /* Low/No Battery */ |
| 180 | struct dptc_input no_battery_input = DPTC_INPUTS( |
| 181 | config->thermctl_limit_degreeC, |
| 182 | config->sustained_power_limit_mW, |
| 183 | config->fast_ppt_limit_mW, |
| 184 | config->slow_ppt_limit_mW, |
| 185 | config->vrm_current_limit_throttle_mA, |
| 186 | config->vrm_maximum_current_limit_throttle_mA, |
| 187 | config->vrm_soc_current_limit_throttle_mA); |
| 188 | acpigen_write_alib_dptc_no_battery((uint8_t *)&no_battery_input, |
| 189 | sizeof(no_battery_input)); |
| 190 | } |
| 191 | |
| 192 | static void root_complex_fill_ssdt(const struct device *device) |
| 193 | { |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 194 | if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)) |
| 195 | acipgen_dptci(); |
| 196 | } |
| 197 | |
| 198 | static const char *gnb_acpi_name(const struct device *dev) |
| 199 | { |
| 200 | return "GNB"; |
| 201 | } |
| 202 | |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 203 | struct device_operations phoenix_root_complex_operations = { |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 204 | /* The root complex has no PCI BARs implemented, so there's no need to call |
| 205 | pci_dev_read_resources for it */ |
| 206 | .read_resources = noop_read_resources, |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 207 | .set_resources = noop_set_resources, |
| 208 | .enable_resources = pci_dev_enable_resources, |
| 209 | .init = root_complex_init, |
| 210 | .acpi_name = gnb_acpi_name, |
| 211 | .acpi_fill_ssdt = root_complex_fill_ssdt, |
| 212 | }; |
Felix Held | e0850ad | 2023-07-18 20:37:50 +0200 | [diff] [blame] | 213 | |
| 214 | uint32_t get_iohc_misc_smn_base(struct device *domain) |
| 215 | { |
Felix Held | 69ffebf | 2023-07-24 21:31:44 +0200 | [diff] [blame] | 216 | return SMN_IOHC_MISC_BASE_13B1; |
Felix Held | e0850ad | 2023-07-18 20:37:50 +0200 | [diff] [blame] | 217 | } |
| 218 | |
| 219 | static const struct non_pci_mmio_reg non_pci_mmio[] = { |
| 220 | { 0x2d0, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 221 | { 0x2d8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 222 | { 0x2e0, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 223 | { 0x2e8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 224 | /* The hardware has a 256 byte alignment requirement for the IOAPIC MMIO base, but we |
| 225 | tell the FSP to configure a 4k-aligned base address and this is reported as 4 KiB |
| 226 | resource. */ |
| 227 | { 0x2f0, 0xffffffffff00ull, 4 * KiB, IOMMU_IOAPIC_IDX }, |
| 228 | { 0x2f8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 229 | { 0x300, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 230 | { 0x308, 0xfffffffff000ull, 4 * KiB, NON_PCI_RES_IDX_AUTO }, |
| 231 | { 0x310, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 232 | { 0x318, 0xfffffff80000ull, 512 * KiB, NON_PCI_RES_IDX_AUTO }, |
| 233 | { 0x320, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 234 | }; |
| 235 | |
| 236 | const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count) |
| 237 | { |
| 238 | *count = ARRAY_SIZE(non_pci_mmio); |
| 239 | return non_pci_mmio; |
| 240 | } |
Felix Held | b0ab545 | 2023-08-11 22:24:00 +0200 | [diff] [blame] | 241 | |
| 242 | signed int get_iohc_fabric_id(struct device *domain) |
| 243 | { |
| 244 | switch (domain->path.domain.domain) { |
| 245 | case 0: |
| 246 | return IOMS0_FABRIC_ID; |
| 247 | default: |
| 248 | return -1; |
| 249 | } |
| 250 | } |