Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | /* TODO: Check if this is still correct */ |
| 4 | |
| 5 | #include <acpi/acpigen.h> |
| 6 | #include <amdblocks/acpi.h> |
| 7 | #include <amdblocks/alib.h> |
Arthur Heymans | ce17972 | 2023-06-07 15:27:18 +0200 | [diff] [blame] | 8 | #include <amdblocks/data_fabric.h> |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 9 | #include <amdblocks/ioapic.h> |
Felix Held | 12a4482 | 2023-06-02 15:30:50 +0200 | [diff] [blame] | 10 | #include <amdblocks/iomap.h> |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 11 | #include <amdblocks/memmap.h> |
Felix Held | 81c81e3 | 2023-07-18 20:37:36 +0200 | [diff] [blame] | 12 | #include <amdblocks/root_complex.h> |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 13 | #include <arch/ioapic.h> |
Felix Held | a4ced63 | 2023-06-05 21:22:15 +0200 | [diff] [blame] | 14 | #include <arch/vga.h> |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 15 | #include <cbmem.h> |
| 16 | #include <console/console.h> |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 17 | #include <device/device.h> |
| 18 | #include <device/pci.h> |
Tim Van Patten | f5ae1dd | 2023-03-31 17:31:10 -0600 | [diff] [blame] | 19 | #include <fsp/amd_misc_data.h> |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 20 | #include <soc/iomap.h> |
| 21 | #include <stdint.h> |
| 22 | #include "chip.h" |
| 23 | |
Tim Van Patten | f5ae1dd | 2023-03-31 17:31:10 -0600 | [diff] [blame] | 24 | #define TDP_15W 15 |
Chris Wang | 50aa3d9 | 2023-02-20 10:27:50 +0800 | [diff] [blame] | 25 | #define DPTC_TOTAL_UPDATE_PARAMS 13 |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 26 | |
| 27 | struct dptc_input { |
| 28 | uint16_t size; |
| 29 | struct alib_dptc_param params[DPTC_TOTAL_UPDATE_PARAMS]; |
| 30 | } __packed; |
| 31 | |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 32 | |
Chris Wang | 50aa3d9 | 2023-02-20 10:27:50 +0800 | [diff] [blame] | 33 | #define DPTC_INPUTS(_thermctllmit, _spptTimeConst, _fast, _slow, \ |
| 34 | _vrmCurrentLimit, _vrmMaxCurrentLimit, _vrmSocCurrentLimit, \ |
Chris Wang | eede5a2 | 2023-02-20 09:43:38 +0800 | [diff] [blame] | 35 | _sttMinLimit, _sttM1, _sttM2, _sttCApu, _sttAlphaApu, _sttSkinTempLimitApu) \ |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 36 | { \ |
| 37 | .size = sizeof(struct dptc_input), \ |
| 38 | .params = { \ |
| 39 | { \ |
| 40 | .id = ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID, \ |
| 41 | .value = _thermctllmit, \ |
| 42 | }, \ |
| 43 | { \ |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 44 | .id = ALIB_DPTC_SLOW_PPT_TIME_CONSTANT_ID, \ |
| 45 | .value = _spptTimeConst, \ |
| 46 | }, \ |
| 47 | { \ |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 48 | .id = ALIB_DPTC_FAST_PPT_LIMIT_ID, \ |
| 49 | .value = _fast, \ |
| 50 | }, \ |
| 51 | { \ |
| 52 | .id = ALIB_DPTC_SLOW_PPT_LIMIT_ID, \ |
| 53 | .value = _slow, \ |
| 54 | }, \ |
Tim Van Patten | 11ca995 | 2022-09-15 17:08:29 -0600 | [diff] [blame] | 55 | { \ |
| 56 | .id = ALIB_DPTC_VRM_CURRENT_LIMIT_ID, \ |
| 57 | .value = _vrmCurrentLimit, \ |
| 58 | }, \ |
| 59 | { \ |
| 60 | .id = ALIB_DPTC_VRM_MAXIMUM_CURRENT_LIMIT, \ |
| 61 | .value = _vrmMaxCurrentLimit, \ |
| 62 | }, \ |
| 63 | { \ |
| 64 | .id = ALIB_DPTC_VRM_SOC_CURRENT_LIMIT_ID, \ |
| 65 | .value = _vrmSocCurrentLimit, \ |
| 66 | }, \ |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 67 | { \ |
| 68 | .id = ALIB_DPTC_STT_MIN_LIMIT_ID, \ |
| 69 | .value = _sttMinLimit, \ |
| 70 | }, \ |
| 71 | { \ |
| 72 | .id = ALIB_DPTC_STT_M1_ID, \ |
| 73 | .value = _sttM1, \ |
| 74 | }, \ |
| 75 | { \ |
| 76 | .id = ALIB_DPTC_STT_M2_ID, \ |
| 77 | .value = _sttM2, \ |
| 78 | }, \ |
| 79 | { \ |
| 80 | .id = ALIB_DPTC_STT_C_APU_ID, \ |
| 81 | .value = _sttCApu, \ |
| 82 | }, \ |
| 83 | { \ |
Chris Wang | eede5a2 | 2023-02-20 09:43:38 +0800 | [diff] [blame] | 84 | .id = ALIB_DPTC_STT_ALPHA_APU, \ |
| 85 | .value = _sttAlphaApu, \ |
| 86 | }, \ |
| 87 | { \ |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 88 | .id = ALIB_DPTC_STT_SKIN_TEMPERATURE_LIMIT_APU_ID, \ |
| 89 | .value = _sttSkinTempLimitApu, \ |
| 90 | }, \ |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 91 | }, \ |
| 92 | } |
| 93 | |
| 94 | /* |
| 95 | * |
| 96 | * +--------------------------------+ |
| 97 | * | | |
| 98 | * | | |
| 99 | * | | |
| 100 | * | | |
| 101 | * | | |
| 102 | * | | |
| 103 | * | | |
| 104 | * reserved_dram_end +--------------------------------+ |
| 105 | * | | |
| 106 | * | verstage (if reqd) | |
| 107 | * | (VERSTAGE_SIZE) | |
| 108 | * +--------------------------------+ VERSTAGE_ADDR |
| 109 | * | | |
| 110 | * | FSP-M | |
| 111 | * | (FSP_M_SIZE) | |
| 112 | * +--------------------------------+ FSP_M_ADDR |
| 113 | * | romstage | |
| 114 | * | (ROMSTAGE_SIZE) | |
| 115 | * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END |
| 116 | * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 |
| 117 | * | bootblock | |
| 118 | * | (C_ENV_BOOTBLOCK_SIZE) | |
| 119 | * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE |
| 120 | * | Unused hole | |
Fred Reitberger | fdb0758 | 2022-07-15 08:05:56 -0400 | [diff] [blame] | 121 | * | (30KiB) | |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 122 | * +--------------------------------+ |
| 123 | * | FMAP cache (FMAP_SIZE) | |
| 124 | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 |
| 125 | * | Early Timestamp region (512B) | |
| 126 | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE |
| 127 | * | Preram CBMEM console | |
| 128 | * | (PRERAM_CBMEM_CONSOLE_SIZE) | |
| 129 | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE |
| 130 | * | PSP shared (vboot workbuf) | |
| 131 | * | (PSP_SHAREDMEM_SIZE) | |
| 132 | * +--------------------------------+ PSP_SHAREDMEM_BASE |
Fred Reitberger | fdb0758 | 2022-07-15 08:05:56 -0400 | [diff] [blame] | 133 | * | APOB (120KiB) | |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 134 | * +--------------------------------+ PSP_APOB_DRAM_ADDRESS |
| 135 | * | Early BSP stack | |
| 136 | * | (EARLYRAM_BSP_STACK_SIZE) | |
| 137 | * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE |
| 138 | * | DRAM | |
| 139 | * +--------------------------------+ 0x100000 |
| 140 | * | Option ROM | |
| 141 | * +--------------------------------+ 0xc0000 |
| 142 | * | Legacy VGA | |
| 143 | * +--------------------------------+ 0xa0000 |
| 144 | * | DRAM | |
| 145 | * +--------------------------------+ 0x0 |
| 146 | */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 147 | void read_soc_memmap_resources(struct device *dev, unsigned long *idx) |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 148 | { |
| 149 | uint32_t mem_usable = (uintptr_t)cbmem_top(); |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 150 | |
| 151 | uintptr_t early_reserved_dram_start, early_reserved_dram_end; |
| 152 | const struct memmap_early_dram *e = memmap_get_early_dram_usage(); |
| 153 | |
| 154 | early_reserved_dram_start = e->base; |
| 155 | early_reserved_dram_end = e->base + e->size; |
| 156 | |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 157 | fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); |
Felix Held | d0959dc | 2023-05-10 15:07:47 +0200 | [diff] [blame] | 158 | |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 159 | /* 0x0 - 0x9ffff */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 160 | ram_range(dev, (*idx)++, 0, 0xa0000); |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 161 | |
| 162 | /* 0xa0000 - 0xbffff: legacy VGA */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 163 | mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 164 | |
| 165 | /* 0xc0000 - 0xfffff: Option ROM */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 166 | reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 167 | |
| 168 | /* 1MiB - bottom of DRAM reserved for early coreboot usage */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 169 | ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 170 | |
| 171 | /* DRAM reserved for early coreboot usage */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 172 | reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 173 | |
| 174 | /* |
| 175 | * top of DRAM consumed early - low top usable RAM |
| 176 | * cbmem_top() accounts for low UMA and TSEG if they are used. |
| 177 | */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 178 | ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 179 | |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 180 | mmconf_resource(dev, (*idx)++); |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 181 | |
Felix Held | 12a4482 | 2023-06-02 15:30:50 +0200 | [diff] [blame] | 182 | /* Reserve fixed IOMMU MMIO region */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 183 | mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); |
Felix Held | 12a4482 | 2023-06-02 15:30:50 +0200 | [diff] [blame] | 184 | |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 185 | read_fsp_resources(dev, idx); |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 186 | } |
| 187 | |
| 188 | static void root_complex_init(struct device *dev) |
| 189 | { |
Kyösti Mälkki | 2e65e9c | 2021-06-16 11:00:40 +0300 | [diff] [blame] | 190 | register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 191 | } |
| 192 | |
| 193 | static void acipgen_dptci(void) |
| 194 | { |
Jon Murphy | 4f73242 | 2022-08-05 15:43:44 -0600 | [diff] [blame] | 195 | const struct soc_amd_mendocino_config *config = config_of_soc(); |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 196 | |
Tim Van Patten | 53ba14d | 2022-09-13 15:42:01 -0600 | [diff] [blame] | 197 | /* Normal mode DPTC values. */ |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 198 | struct dptc_input default_input = DPTC_INPUTS( |
| 199 | config->thermctl_limit_degreeC, |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 200 | config->slow_ppt_time_constant_s, |
Tim Van Patten | 9244358 | 2022-08-23 16:06:33 -0600 | [diff] [blame] | 201 | config->fast_ppt_limit_mW, |
Tim Van Patten | 11ca995 | 2022-09-15 17:08:29 -0600 | [diff] [blame] | 202 | config->slow_ppt_limit_mW, |
| 203 | config->vrm_current_limit_mA, |
| 204 | config->vrm_maximum_current_limit_mA, |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 205 | config->vrm_soc_current_limit_mA, |
| 206 | config->stt_min_limit, |
| 207 | config->stt_m1, |
| 208 | config->stt_m2, |
| 209 | config->stt_c_apu, |
Chris Wang | eede5a2 | 2023-02-20 09:43:38 +0800 | [diff] [blame] | 210 | config->stt_alpha_apu, |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 211 | config->stt_skin_temp_apu); |
Tim Van Patten | 9244358 | 2022-08-23 16:06:33 -0600 | [diff] [blame] | 212 | acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input)); |
Tim Van Patten | 1075fef | 2022-05-20 11:06:03 -0600 | [diff] [blame] | 213 | |
| 214 | /* Low/No Battery */ |
| 215 | struct dptc_input no_battery_input = DPTC_INPUTS( |
| 216 | config->thermctl_limit_degreeC, |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 217 | config->slow_ppt_time_constant_s, |
Tim Van Patten | 1075fef | 2022-05-20 11:06:03 -0600 | [diff] [blame] | 218 | config->fast_ppt_limit_mW, |
| 219 | config->slow_ppt_limit_mW, |
| 220 | config->vrm_current_limit_throttle_mA, |
| 221 | config->vrm_maximum_current_limit_throttle_mA, |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 222 | config->vrm_soc_current_limit_throttle_mA, |
| 223 | config->stt_min_limit, |
| 224 | config->stt_m1, |
| 225 | config->stt_m2, |
| 226 | config->stt_c_apu, |
Chris Wang | eede5a2 | 2023-02-20 09:43:38 +0800 | [diff] [blame] | 227 | config->stt_alpha_apu, |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 228 | config->stt_skin_temp_apu); |
Tim Van Patten | 1075fef | 2022-05-20 11:06:03 -0600 | [diff] [blame] | 229 | acpigen_write_alib_dptc_no_battery((uint8_t *)&no_battery_input, |
| 230 | sizeof(no_battery_input)); |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 231 | |
Chris.Wang | 9ac0984 | 2022-12-13 14:31:38 +0800 | [diff] [blame] | 232 | #if (CONFIG(FEATURE_TABLET_MODE_DPTC)) |
| 233 | struct dptc_input tablet_input = DPTC_INPUTS( |
| 234 | config->thermctl_limit_degreeC, |
Chris.Wang | 9ac0984 | 2022-12-13 14:31:38 +0800 | [diff] [blame] | 235 | config->slow_ppt_time_constant_s, |
| 236 | config->fast_ppt_limit_mW, |
| 237 | config->slow_ppt_limit_mW, |
| 238 | config->vrm_current_limit_mA, |
| 239 | config->vrm_maximum_current_limit_mA, |
| 240 | config->vrm_soc_current_limit_mA, |
| 241 | config->stt_min_limit, |
Chris Wang | 2809507 | 2023-02-23 16:25:52 +0800 | [diff] [blame] | 242 | config->stt_m1_tablet, |
| 243 | config->stt_m2_tablet, |
| 244 | config->stt_c_apu_tablet, |
| 245 | config->stt_alpha_apu_tablet, |
Chris.Wang | 9ac0984 | 2022-12-13 14:31:38 +0800 | [diff] [blame] | 246 | config->stt_skin_temp_apu); |
| 247 | acpigen_write_alib_dptc_tablet((uint8_t *)&tablet_input, sizeof(tablet_input)); |
| 248 | #endif |
| 249 | |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 250 | #if (CONFIG(FEATURE_DYNAMIC_DPTC)) |
| 251 | /* Profile B */ |
| 252 | struct dptc_input thermal_B_input = DPTC_INPUTS( |
| 253 | config->thermctl_limit_degreeC, |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 254 | config->slow_ppt_time_constant_s_B, |
| 255 | config->fast_ppt_limit_mW_B, |
| 256 | config->slow_ppt_limit_mW_B, |
| 257 | config->vrm_current_limit_throttle_mA, |
| 258 | config->vrm_maximum_current_limit_mA, |
| 259 | config->vrm_soc_current_limit_mA, |
| 260 | config->stt_min_limit_B, |
| 261 | config->stt_m1_B, |
| 262 | config->stt_m2_B, |
| 263 | config->stt_c_apu_B, |
Chris Wang | eede5a2 | 2023-02-20 09:43:38 +0800 | [diff] [blame] | 264 | config->stt_alpha_apu, |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 265 | config->stt_skin_temp_apu_B); |
| 266 | acpigen_write_alib_dptc_thermal_B((uint8_t *)&thermal_B_input, |
| 267 | sizeof(thermal_B_input)); |
| 268 | |
| 269 | /* Profile C */ |
| 270 | struct dptc_input thermal_C_input = DPTC_INPUTS( |
| 271 | config->thermctl_limit_degreeC, |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 272 | config->slow_ppt_time_constant_s_C, |
| 273 | config->fast_ppt_limit_mW_C, |
| 274 | config->slow_ppt_limit_mW_C, |
| 275 | config->vrm_current_limit_mA, |
| 276 | config->vrm_maximum_current_limit_mA, |
| 277 | config->vrm_soc_current_limit_mA, |
| 278 | config->stt_min_limit_C, |
| 279 | config->stt_m1_C, |
| 280 | config->stt_m2_C, |
| 281 | config->stt_c_apu_C, |
Chris Wang | eede5a2 | 2023-02-20 09:43:38 +0800 | [diff] [blame] | 282 | config->stt_alpha_apu, |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 283 | config->stt_skin_temp_apu_C); |
| 284 | acpigen_write_alib_dptc_thermal_C((uint8_t *)&thermal_C_input, |
| 285 | sizeof(thermal_C_input)); |
| 286 | |
| 287 | /* Profile D */ |
| 288 | struct dptc_input thermal_D_input = DPTC_INPUTS( |
| 289 | config->thermctl_limit_degreeC, |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 290 | config->slow_ppt_time_constant_s_D, |
| 291 | config->fast_ppt_limit_mW_D, |
| 292 | config->slow_ppt_limit_mW_D, |
| 293 | config->vrm_current_limit_mA, |
| 294 | config->vrm_maximum_current_limit_mA, |
| 295 | config->vrm_soc_current_limit_mA, |
| 296 | config->stt_min_limit_D, |
| 297 | config->stt_m1_D, |
| 298 | config->stt_m2_D, |
| 299 | config->stt_c_apu_D, |
Chris Wang | eede5a2 | 2023-02-20 09:43:38 +0800 | [diff] [blame] | 300 | config->stt_alpha_apu, |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 301 | config->stt_skin_temp_apu_D); |
| 302 | acpigen_write_alib_dptc_thermal_D((uint8_t *)&thermal_D_input, |
| 303 | sizeof(thermal_D_input)); |
| 304 | |
| 305 | /* Profile E */ |
| 306 | struct dptc_input thermal_E_input = DPTC_INPUTS( |
| 307 | config->thermctl_limit_degreeC, |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 308 | config->slow_ppt_time_constant_s_E, |
| 309 | config->fast_ppt_limit_mW_E, |
| 310 | config->slow_ppt_limit_mW_E, |
| 311 | config->vrm_current_limit_mA, |
| 312 | config->vrm_maximum_current_limit_mA, |
| 313 | config->vrm_soc_current_limit_mA, |
| 314 | config->stt_min_limit_E, |
| 315 | config->stt_m1_E, |
| 316 | config->stt_m2_E, |
| 317 | config->stt_c_apu_E, |
Chris Wang | eede5a2 | 2023-02-20 09:43:38 +0800 | [diff] [blame] | 318 | config->stt_alpha_apu, |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 319 | config->stt_skin_temp_apu_E); |
| 320 | acpigen_write_alib_dptc_thermal_E((uint8_t *)&thermal_E_input, |
| 321 | sizeof(thermal_E_input)); |
| 322 | |
| 323 | /* Profile F */ |
| 324 | struct dptc_input thermal_F_input = DPTC_INPUTS( |
| 325 | config->thermctl_limit_degreeC, |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 326 | config->slow_ppt_time_constant_s_F, |
| 327 | config->fast_ppt_limit_mW_F, |
| 328 | config->slow_ppt_limit_mW_F, |
| 329 | config->vrm_current_limit_mA, |
| 330 | config->vrm_maximum_current_limit_mA, |
| 331 | config->vrm_soc_current_limit_mA, |
| 332 | config->stt_min_limit_F, |
| 333 | config->stt_m1_F, |
| 334 | config->stt_m2_F, |
| 335 | config->stt_c_apu_F, |
Chris Wang | eede5a2 | 2023-02-20 09:43:38 +0800 | [diff] [blame] | 336 | config->stt_alpha_apu, |
EricKY Cheng | 33e0df1 | 2022-10-21 19:35:30 +0800 | [diff] [blame] | 337 | config->stt_skin_temp_apu_F); |
| 338 | acpigen_write_alib_dptc_thermal_F((uint8_t *)&thermal_F_input, |
| 339 | sizeof(thermal_F_input)); |
| 340 | #endif |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 341 | } |
| 342 | |
| 343 | static void root_complex_fill_ssdt(const struct device *device) |
| 344 | { |
Tim Van Patten | f5ae1dd | 2023-03-31 17:31:10 -0600 | [diff] [blame] | 345 | uint32_t tdp = 0; |
| 346 | |
Tim Van Patten | f5ae1dd | 2023-03-31 17:31:10 -0600 | [diff] [blame] | 347 | if (get_amd_smu_reported_tdp(&tdp) != CB_SUCCESS) { |
| 348 | /* Unknown TDP, so return rather than setting invalid values. */ |
| 349 | return; |
| 350 | } |
| 351 | /* TODO(b/249359574): Add support for 6W DPTC values. */ |
| 352 | if (tdp != TDP_15W) |
| 353 | return; |
| 354 | |
Tim Van Patten | 53ba14d | 2022-09-13 15:42:01 -0600 | [diff] [blame] | 355 | if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)) |
| 356 | acipgen_dptci(); |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 357 | } |
| 358 | |
| 359 | static const char *gnb_acpi_name(const struct device *dev) |
| 360 | { |
| 361 | return "GNB"; |
| 362 | } |
| 363 | |
Arthur Heymans | 6a5d770 | 2022-10-05 14:41:51 +0200 | [diff] [blame] | 364 | struct device_operations mendocino_root_complex_operations = { |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame^] | 365 | /* The root complex has no PCI BARs implemented, so there's no need to call |
| 366 | pci_dev_read_resources for it */ |
| 367 | .read_resources = noop_read_resources, |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 368 | .set_resources = noop_set_resources, |
| 369 | .enable_resources = pci_dev_enable_resources, |
| 370 | .init = root_complex_init, |
| 371 | .acpi_name = gnb_acpi_name, |
| 372 | .acpi_fill_ssdt = root_complex_fill_ssdt, |
| 373 | }; |
Felix Held | 81c81e3 | 2023-07-18 20:37:36 +0200 | [diff] [blame] | 374 | |
| 375 | uint32_t get_iohc_misc_smn_base(struct device *domain) |
| 376 | { |
Felix Held | 69ffebf | 2023-07-24 21:31:44 +0200 | [diff] [blame] | 377 | return SMN_IOHC_MISC_BASE_13B1; |
Felix Held | 81c81e3 | 2023-07-18 20:37:36 +0200 | [diff] [blame] | 378 | } |
| 379 | |
| 380 | static const struct non_pci_mmio_reg non_pci_mmio[] = { |
| 381 | { 0x2d8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 382 | { 0x2e0, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 383 | { 0x2e8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 384 | /* The hardware has a 256 byte alignment requirement for the IOAPIC MMIO base, but we |
| 385 | tell the FSP to configure a 4k-aligned base address and this is reported as 4 KiB |
| 386 | resource. */ |
| 387 | { 0x2f0, 0xffffffffff00ull, 4 * KiB, IOMMU_IOAPIC_IDX }, |
| 388 | { 0x2f8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 389 | { 0x300, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 390 | { 0x308, 0xfffffffff000ull, 4 * KiB, NON_PCI_RES_IDX_AUTO }, |
| 391 | { 0x318, 0xfffffff80000ull, 512 * KiB, NON_PCI_RES_IDX_AUTO }, |
| 392 | }; |
| 393 | |
| 394 | const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count) |
| 395 | { |
| 396 | *count = ARRAY_SIZE(non_pci_mmio); |
| 397 | return non_pci_mmio; |
| 398 | } |
Felix Held | b0ab545 | 2023-08-11 22:24:00 +0200 | [diff] [blame] | 399 | |
| 400 | signed int get_iohc_fabric_id(struct device *domain) |
| 401 | { |
| 402 | switch (domain->path.domain.domain) { |
| 403 | case 0: |
| 404 | return IOMS0_FABRIC_ID; |
| 405 | default: |
| 406 | return -1; |
| 407 | } |
| 408 | } |