Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | |
| 21 | #include <arch/io.h> |
| 22 | #include <arch/romcc_io.h> |
| 23 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 24 | static void sb800_enable_rom(void) |
| 25 | { |
| 26 | u32 word; |
| 27 | u32 dword; |
| 28 | device_t dev; |
| 29 | |
| 30 | dev = PCI_DEV(0, 0x14, 0x03); |
| 31 | /* SB800 LPC Bridge 0:20:3:44h. |
| 32 | * BIT6: Port Enable for serial port 0x3f8-0x3ff |
| 33 | * BIT29: Port Enable for KBC port 0x60 and 0x64 |
| 34 | * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 |
| 35 | */ |
| 36 | dword = pci_io_read_config32(dev, 0x44); |
| 37 | //dword |= (1<<6) | (1<<29) | (1<<30) ; |
Stefan Reinauer | 305f2f5 | 2011-04-20 22:23:56 +0000 | [diff] [blame^] | 38 | /* Turn on all of LPC IO Port decode enable */ |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 39 | dword = 0xffffffff; |
| 40 | pci_io_write_config32(dev, 0x44, dword); |
| 41 | |
| 42 | /* SB800 LPC Bridge 0:20:3:48h. |
| 43 | * BIT0: Port Enable for SuperIO 0x2E-0x2F |
| 44 | * BIT1: Port Enable for SuperIO 0x4E-0x4F |
| 45 | * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C) |
| 46 | * BIT6: Port Enable for RTC IO 0x70-0x73 |
| 47 | * BIT21: Port Enable for Port 0x80 |
| 48 | */ |
| 49 | dword = pci_io_read_config32(dev, 0x48); |
| 50 | dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; |
| 51 | pci_io_write_config32(dev, 0x48, dword); |
| 52 | |
| 53 | /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */ |
| 54 | /* Set the 4MB enable bits */ |
| 55 | word = pci_io_read_config16(dev, 0x6c); |
| 56 | word = 0xFFC0; |
| 57 | pci_io_write_config16(dev, 0x6c, word); |
| 58 | } |
| 59 | |
| 60 | static void bootblock_southbridge_init(void) |
| 61 | { |
| 62 | /* Setup the rom access for 2M */ |
| 63 | sb800_enable_rom(); |
| 64 | } |