Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 3 | |
| 4 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 6 | #include <arch/acpi.h> |
| 7 | #include <stdint.h> |
| 8 | #include <device/device.h> |
| 9 | #include <device/pci.h> |
| 10 | #include <device/pci_ids.h> |
| 11 | #include <device/hypertransport.h> |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 12 | #include <string.h> |
| 13 | #include <lib.h> |
| 14 | #include <cpu/cpu.h> |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 15 | #include <Porting.h> |
| 16 | #include <AGESA.h> |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 17 | #include <Topology.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 18 | #include <cpu/x86/lapic.h> |
| 19 | #include <cpu/amd/msr.h> |
| 20 | #include <cpu/amd/mtrr.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 21 | #include <arch/acpigen.h> |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 22 | #include <northbridge/amd/pi/nb_common.h> |
Kyösti Mälkki | ed8d277 | 2017-07-15 17:12:44 +0300 | [diff] [blame] | 23 | #include <northbridge/amd/agesa/agesa_helper.h> |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 24 | |
Kyösti Mälkki | 113f670 | 2018-05-20 20:12:32 +0300 | [diff] [blame] | 25 | #define MAX_NODE_NUMS MAX_NODES |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 26 | |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 27 | typedef struct dram_base_mask { |
| 28 | u32 base; //[47:27] at [28:8] |
| 29 | u32 mask; //[47:27] at [28:8] and enable at bit 0 |
| 30 | } dram_base_mask_t; |
| 31 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 32 | static unsigned int node_nums; |
| 33 | static unsigned int sblink; |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 34 | static struct device *__f0_dev[MAX_NODE_NUMS]; |
| 35 | static struct device *__f1_dev[MAX_NODE_NUMS]; |
| 36 | static struct device *__f2_dev[MAX_NODE_NUMS]; |
| 37 | static struct device *__f4_dev[MAX_NODE_NUMS]; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 38 | static unsigned int fx_devs = 0; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 39 | |
| 40 | static dram_base_mask_t get_dram_base_mask(u32 nodeid) |
| 41 | { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 42 | struct device *dev; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 43 | dram_base_mask_t d; |
| 44 | dev = __f1_dev[0]; |
| 45 | u32 temp; |
| 46 | temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] |
| 47 | d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too |
| 48 | temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] |
| 49 | d.mask |= temp<<21; |
| 50 | temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] |
| 51 | d.mask |= (temp & 1); // enable bit |
| 52 | d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too |
| 53 | temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] |
| 54 | d.base |= temp<<21; |
| 55 | return d; |
| 56 | } |
| 57 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 58 | static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 59 | u32 io_min, u32 io_max) |
| 60 | { |
| 61 | u32 i; |
| 62 | u32 tempreg; |
| 63 | /* io range allocation */ |
| 64 | tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 65 | for (i = 0; i < node_nums; i++) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 66 | pci_write_config32(__f1_dev[i], reg+4, tempreg); |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 67 | tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? |
| 68 | for (i = 0; i < node_nums; i++) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 69 | pci_write_config32(__f1_dev[i], reg, tempreg); |
| 70 | } |
| 71 | |
| 72 | static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) |
| 73 | { |
| 74 | u32 i; |
| 75 | u32 tempreg; |
| 76 | /* io range allocation */ |
| 77 | tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 78 | for (i = 0; i < nodes; i++) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 79 | pci_write_config32(__f1_dev[i], reg+4, tempreg); |
| 80 | tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 81 | for (i = 0; i < node_nums; i++) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 82 | pci_write_config32(__f1_dev[i], reg, tempreg); |
| 83 | } |
| 84 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 85 | static struct device *get_node_pci(u32 nodeid, u32 fn) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 86 | { |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 87 | return pcidev_on_root(DEV_CDB + nodeid, fn); |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 88 | } |
| 89 | |
| 90 | static void get_fx_devs(void) |
| 91 | { |
| 92 | int i; |
| 93 | for (i = 0; i < MAX_NODE_NUMS; i++) { |
| 94 | __f0_dev[i] = get_node_pci(i, 0); |
| 95 | __f1_dev[i] = get_node_pci(i, 1); |
| 96 | __f2_dev[i] = get_node_pci(i, 2); |
| 97 | __f4_dev[i] = get_node_pci(i, 4); |
| 98 | if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) |
| 99 | fx_devs = i+1; |
| 100 | } |
| 101 | if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { |
| 102 | die("Cannot find 0:0x18.[0|1]\n"); |
| 103 | } |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 104 | printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 105 | } |
| 106 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 107 | static u32 f1_read_config32(unsigned int reg) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 108 | { |
| 109 | if (fx_devs == 0) |
| 110 | get_fx_devs(); |
| 111 | return pci_read_config32(__f1_dev[0], reg); |
| 112 | } |
| 113 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 114 | static void f1_write_config32(unsigned int reg, u32 value) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 115 | { |
| 116 | int i; |
| 117 | if (fx_devs == 0) |
| 118 | get_fx_devs(); |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 119 | for (i = 0; i < fx_devs; i++) { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 120 | struct device *dev; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 121 | dev = __f1_dev[i]; |
| 122 | if (dev && dev->enabled) { |
| 123 | pci_write_config32(dev, reg, value); |
| 124 | } |
| 125 | } |
| 126 | } |
| 127 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 128 | static u32 amdfam15_nodeid(struct device *dev) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 129 | { |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 130 | return (dev->path.pci.devfn >> 3) - DEV_CDB; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 131 | } |
| 132 | |
| 133 | static void set_vga_enable_reg(u32 nodeid, u32 linkn) |
| 134 | { |
| 135 | u32 val; |
| 136 | |
| 137 | val = 1 | (nodeid<<4) | (linkn<<12); |
| 138 | /* it will routing |
| 139 | * (1)mmio 0xa0000:0xbffff |
| 140 | * (2)io 0x3b0:0x3bb, 0x3c0:0x3df |
| 141 | */ |
| 142 | f1_write_config32(0xf4, val); |
| 143 | |
| 144 | } |
| 145 | |
| 146 | /** |
| 147 | * @return |
| 148 | * @retval 2 resource does not exist, usable |
| 149 | * @retval 0 resource exists, but is not usable |
| 150 | * @retval 1 resource exists, but has been allocated before |
| 151 | */ |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 152 | static int reg_useable(unsigned int reg, struct device *goal_dev, |
| 153 | unsigned int goal_nodeid, unsigned int goal_link) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 154 | { |
| 155 | struct resource *res; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 156 | unsigned int nodeid, link = 0; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 157 | int result; |
| 158 | res = 0; |
| 159 | for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 160 | struct device *dev; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 161 | dev = __f0_dev[nodeid]; |
| 162 | if (!dev) |
| 163 | continue; |
| 164 | for (link = 0; !res && (link < 8); link++) { |
| 165 | res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 166 | } |
| 167 | } |
| 168 | result = 2; |
| 169 | if (res) { |
| 170 | result = 0; |
| 171 | if ((goal_link == (link - 1)) && |
| 172 | (goal_nodeid == (nodeid - 1)) && |
| 173 | (res->flags <= 1)) { |
| 174 | result = 1; |
| 175 | } |
| 176 | } |
| 177 | return result; |
| 178 | } |
| 179 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 180 | static struct resource *amdfam15_find_iopair(struct device *dev, |
| 181 | unsigned int nodeid, unsigned int link) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 182 | { |
| 183 | struct resource *resource; |
| 184 | u32 free_reg, reg; |
| 185 | resource = 0; |
| 186 | free_reg = 0; |
| 187 | for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { |
| 188 | int result; |
| 189 | result = reg_useable(reg, dev, nodeid, link); |
| 190 | if (result == 1) { |
| 191 | /* I have been allocated this one */ |
| 192 | break; |
| 193 | } |
| 194 | else if (result > 1) { |
| 195 | /* I have a free register pair */ |
| 196 | free_reg = reg; |
| 197 | } |
| 198 | } |
| 199 | if (reg > 0xd8) { |
| 200 | reg = free_reg; // if no free, the free_reg still be 0 |
| 201 | } |
| 202 | |
| 203 | resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 204 | |
| 205 | return resource; |
| 206 | } |
| 207 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 208 | static struct resource *amdfam15_find_mempair(struct device *dev, u32 nodeid, u32 link) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 209 | { |
| 210 | struct resource *resource; |
| 211 | u32 free_reg, reg; |
| 212 | resource = 0; |
| 213 | free_reg = 0; |
| 214 | for (reg = 0x80; reg <= 0xb8; reg += 0x8) { |
| 215 | int result; |
| 216 | result = reg_useable(reg, dev, nodeid, link); |
| 217 | if (result == 1) { |
| 218 | /* I have been allocated this one */ |
| 219 | break; |
| 220 | } |
| 221 | else if (result > 1) { |
| 222 | /* I have a free register pair */ |
| 223 | free_reg = reg; |
| 224 | } |
| 225 | } |
| 226 | if (reg > 0xb8) { |
| 227 | reg = free_reg; |
| 228 | } |
| 229 | |
| 230 | resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 231 | return resource; |
| 232 | } |
| 233 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 234 | static void amdfam15_link_read_bases(struct device *dev, u32 nodeid, u32 link) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 235 | { |
| 236 | struct resource *resource; |
| 237 | |
| 238 | /* Initialize the io space constraints on the current bus */ |
| 239 | resource = amdfam15_find_iopair(dev, nodeid, link); |
| 240 | if (resource) { |
| 241 | u32 align; |
| 242 | align = log2(HT_IO_HOST_ALIGN); |
| 243 | resource->base = 0; |
| 244 | resource->size = 0; |
| 245 | resource->align = align; |
| 246 | resource->gran = align; |
| 247 | resource->limit = 0xffffUL; |
| 248 | resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; |
| 249 | } |
| 250 | |
| 251 | /* Initialize the prefetchable memory constraints on the current bus */ |
| 252 | resource = amdfam15_find_mempair(dev, nodeid, link); |
| 253 | if (resource) { |
| 254 | resource->base = 0; |
| 255 | resource->size = 0; |
| 256 | resource->align = log2(HT_MEM_HOST_ALIGN); |
| 257 | resource->gran = log2(HT_MEM_HOST_ALIGN); |
| 258 | resource->limit = 0xffffffffffULL; |
| 259 | resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; |
| 260 | resource->flags |= IORESOURCE_BRIDGE; |
| 261 | } |
| 262 | |
| 263 | /* Initialize the memory constraints on the current bus */ |
| 264 | resource = amdfam15_find_mempair(dev, nodeid, link); |
| 265 | if (resource) { |
| 266 | resource->base = 0; |
| 267 | resource->size = 0; |
| 268 | resource->align = log2(HT_MEM_HOST_ALIGN); |
| 269 | resource->gran = log2(HT_MEM_HOST_ALIGN); |
| 270 | resource->limit = 0xffffffffffULL; |
| 271 | resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; |
| 272 | } |
| 273 | |
| 274 | } |
| 275 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 276 | static void read_resources(struct device *dev) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 277 | { |
| 278 | u32 nodeid; |
| 279 | struct bus *link; |
| 280 | |
| 281 | nodeid = amdfam15_nodeid(dev); |
| 282 | for (link = dev->link_list; link; link = link->next) { |
| 283 | if (link->children) { |
| 284 | amdfam15_link_read_bases(dev, nodeid, link->link_num); |
| 285 | } |
| 286 | } |
| 287 | |
| 288 | /* |
| 289 | * This MMCONF resource must be reserved in the PCI domain. |
| 290 | * It is not honored by the coreboot resource allocator if it is in |
| 291 | * the CPU_CLUSTER. |
| 292 | */ |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 293 | mmconf_resource(dev, MMIO_CONF_BASE); |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 294 | } |
| 295 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 296 | static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 297 | { |
| 298 | resource_t rbase, rend; |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 299 | unsigned int reg, link_num; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 300 | char buf[50]; |
| 301 | |
| 302 | /* Make certain the resource has actually been set */ |
| 303 | if (!(resource->flags & IORESOURCE_ASSIGNED)) { |
| 304 | return; |
| 305 | } |
| 306 | |
| 307 | /* If I have already stored this resource don't worry about it */ |
| 308 | if (resource->flags & IORESOURCE_STORED) { |
| 309 | return; |
| 310 | } |
| 311 | |
| 312 | /* Only handle PCI memory and IO resources */ |
| 313 | if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) |
| 314 | return; |
| 315 | |
| 316 | /* Ensure I am actually looking at a resource of function 1 */ |
| 317 | if ((resource->index & 0xffff) < 0x1000) { |
| 318 | return; |
| 319 | } |
| 320 | /* Get the base address */ |
| 321 | rbase = resource->base; |
| 322 | |
| 323 | /* Get the limit (rounded up) */ |
| 324 | rend = resource_end(resource); |
| 325 | |
| 326 | /* Get the register and link */ |
| 327 | reg = resource->index & 0xfff; // 4k |
| 328 | link_num = IOINDEX_LINK(resource->index); |
| 329 | |
| 330 | if (resource->flags & IORESOURCE_IO) { |
| 331 | set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); |
| 332 | } |
| 333 | else if (resource->flags & IORESOURCE_MEM) { |
Elyes HAOUAS | 7db506c | 2016-10-02 11:56:39 +0200 | [diff] [blame] | 334 | set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums); // [39:8] |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 335 | } |
| 336 | resource->flags |= IORESOURCE_STORED; |
Elyes HAOUAS | 0d4b11a | 2016-10-03 21:57:21 +0200 | [diff] [blame] | 337 | snprintf(buf, sizeof(buf), " <node %x link %x>", |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 338 | nodeid, link_num); |
| 339 | report_resource_stored(dev, resource, buf); |
| 340 | } |
| 341 | |
| 342 | /** |
| 343 | * I tried to reuse the resource allocation code in set_resource() |
| 344 | * but it is too difficult to deal with the resource allocation magic. |
| 345 | */ |
| 346 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 347 | static void create_vga_resource(struct device *dev, unsigned int nodeid) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 348 | { |
| 349 | struct bus *link; |
| 350 | |
| 351 | /* find out which link the VGA card is connected, |
| 352 | * we only deal with the 'first' vga card */ |
| 353 | for (link = dev->link_list; link; link = link->next) { |
| 354 | if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 355 | if (CONFIG(MULTIPLE_VGA_ADAPTERS)) { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 356 | extern struct device *vga_pri; // the primary vga device, defined in device.c |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 357 | printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, |
| 358 | link->secondary,link->subordinate); |
| 359 | /* We need to make sure the vga_pri is under the link */ |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 360 | if ((vga_pri->bus->secondary >= link->secondary) && |
| 361 | (vga_pri->bus->secondary <= link->subordinate)) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 362 | break; |
| 363 | } |
| 364 | else |
| 365 | break; |
| 366 | } |
| 367 | } |
| 368 | |
| 369 | /* no VGA card installed */ |
| 370 | if (link == NULL) |
| 371 | return; |
| 372 | |
| 373 | printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); |
| 374 | set_vga_enable_reg(nodeid, sblink); |
| 375 | } |
| 376 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 377 | static void set_resources(struct device *dev) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 378 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 379 | unsigned int nodeid; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 380 | struct bus *bus; |
| 381 | struct resource *res; |
| 382 | |
| 383 | /* Find the nodeid */ |
| 384 | nodeid = amdfam15_nodeid(dev); |
| 385 | |
| 386 | create_vga_resource(dev, nodeid); //TODO: do we need this? |
| 387 | |
| 388 | /* Set each resource we have found */ |
| 389 | for (res = dev->resource_list; res; res = res->next) { |
| 390 | set_resource(dev, res, nodeid); |
| 391 | } |
| 392 | |
| 393 | for (bus = dev->link_list; bus; bus = bus->next) { |
| 394 | if (bus->children) { |
| 395 | assign_resources(bus); |
| 396 | } |
| 397 | } |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 398 | } |
| 399 | |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 400 | static unsigned long acpi_fill_hest(acpi_hest_t *hest) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 401 | { |
| 402 | void *addr, *current; |
| 403 | |
| 404 | /* Skip the HEST header. */ |
| 405 | current = (void *)(hest + 1); |
| 406 | |
| 407 | addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); |
| 408 | if (addr != NULL) |
| 409 | current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 410 | |
| 411 | addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); |
| 412 | if (addr != NULL) |
| 413 | current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 414 | |
| 415 | return (unsigned long)current; |
| 416 | } |
| 417 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 418 | static void northbridge_fill_ssdt_generator(struct device *device) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 419 | { |
| 420 | msr_t msr; |
| 421 | char pscope[] = "\\_SB.PCI0"; |
| 422 | |
| 423 | acpigen_write_scope(pscope); |
| 424 | msr = rdmsr(TOP_MEM); |
| 425 | acpigen_write_name_dword("TOM1", msr.lo); |
| 426 | msr = rdmsr(TOP_MEM2); |
| 427 | /* |
| 428 | * Since XP only implements parts of ACPI 2.0, we can't use a qword |
| 429 | * here. |
| 430 | * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt |
| 431 | * slide 22ff. |
| 432 | * Shift value right by 20 bit to make it fit into 32bit, |
| 433 | * giving us 1MB granularity and a limit of almost 4Exabyte of memory. |
| 434 | */ |
| 435 | acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); |
| 436 | acpigen_pop_len(); |
| 437 | } |
| 438 | |
Michał Żygowski | 9550e97 | 2020-03-20 13:56:46 +0100 | [diff] [blame] | 439 | static void patch_ssdt_processor_scope(acpi_header_t *ssdt) |
| 440 | { |
| 441 | unsigned int len = ssdt->length - sizeof(acpi_header_t); |
| 442 | unsigned int i; |
| 443 | |
| 444 | for (i = sizeof(acpi_header_t); i < len; i++) { |
| 445 | /* Search for _PR_ scope and replace it with _SB_ */ |
| 446 | if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f) |
| 447 | *(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f; |
| 448 | } |
| 449 | /* Recalculate checksum */ |
| 450 | ssdt->checksum = 0; |
| 451 | ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); |
| 452 | } |
| 453 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 454 | static unsigned long agesa_write_acpi_tables(struct device *device, |
Alexander Couzens | 83fc32f | 2015-04-12 22:28:37 +0200 | [diff] [blame] | 455 | unsigned long current, |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 456 | acpi_rsdp_t *rsdp) |
| 457 | { |
| 458 | acpi_srat_t *srat; |
| 459 | acpi_slit_t *slit; |
| 460 | acpi_header_t *ssdt; |
| 461 | acpi_header_t *alib; |
| 462 | acpi_header_t *ivrs; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 463 | |
| 464 | /* HEST */ |
| 465 | current = ALIGN(current, 8); |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 466 | acpi_write_hest((void *)current, acpi_fill_hest); |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 467 | acpi_add_table(rsdp, (void *)current); |
| 468 | current += ((acpi_header_t *)current)->length; |
| 469 | |
| 470 | current = ALIGN(current, 8); |
| 471 | printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); |
| 472 | ivrs = agesawrapper_getlateinitptr(PICK_IVRS); |
| 473 | if (ivrs != NULL) { |
| 474 | memcpy((void *)current, ivrs, ivrs->length); |
| 475 | ivrs = (acpi_header_t *) current; |
| 476 | current += ivrs->length; |
| 477 | acpi_add_table(rsdp, ivrs); |
| 478 | } else { |
| 479 | printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); |
| 480 | } |
| 481 | |
| 482 | /* SRAT */ |
| 483 | current = ALIGN(current, 8); |
| 484 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
| 485 | srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); |
| 486 | if (srat != NULL) { |
| 487 | memcpy((void *)current, srat, srat->header.length); |
| 488 | srat = (acpi_srat_t *) current; |
| 489 | current += srat->header.length; |
| 490 | acpi_add_table(rsdp, srat); |
| 491 | } else { |
| 492 | printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); |
| 493 | } |
| 494 | |
| 495 | /* SLIT */ |
| 496 | current = ALIGN(current, 8); |
| 497 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
| 498 | slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); |
| 499 | if (slit != NULL) { |
| 500 | memcpy((void *)current, slit, slit->header.length); |
| 501 | slit = (acpi_slit_t *) current; |
| 502 | current += slit->header.length; |
| 503 | acpi_add_table(rsdp, slit); |
| 504 | } else { |
| 505 | printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); |
| 506 | } |
| 507 | |
| 508 | /* ALIB */ |
| 509 | current = ALIGN(current, 16); |
| 510 | printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); |
| 511 | alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); |
| 512 | if (alib != NULL) { |
| 513 | memcpy((void *)current, alib, alib->length); |
| 514 | alib = (acpi_header_t *) current; |
| 515 | current += alib->length; |
| 516 | acpi_add_table(rsdp, (void *)alib); |
| 517 | } |
| 518 | else { |
| 519 | printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); |
| 520 | } |
| 521 | |
| 522 | /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ |
| 523 | /* SSDT */ |
| 524 | current = ALIGN(current, 16); |
| 525 | printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); |
| 526 | ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); |
| 527 | if (ssdt != NULL) { |
Michał Żygowski | 9550e97 | 2020-03-20 13:56:46 +0100 | [diff] [blame] | 528 | patch_ssdt_processor_scope(ssdt); |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 529 | memcpy((void *)current, ssdt, ssdt->length); |
| 530 | ssdt = (acpi_header_t *) current; |
| 531 | current += ssdt->length; |
| 532 | } |
| 533 | else { |
| 534 | printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); |
| 535 | } |
| 536 | acpi_add_table(rsdp,ssdt); |
| 537 | |
| 538 | printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); |
| 539 | return current; |
| 540 | } |
| 541 | |
| 542 | static struct device_operations northbridge_operations = { |
| 543 | .read_resources = read_resources, |
| 544 | .set_resources = set_resources, |
| 545 | .enable_resources = pci_dev_enable_resources, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 546 | .acpi_fill_ssdt = northbridge_fill_ssdt_generator, |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 547 | .write_acpi_tables = agesa_write_acpi_tables, |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 548 | }; |
| 549 | |
| 550 | static const struct pci_driver family15_northbridge __pci_driver = { |
| 551 | .ops = &northbridge_operations, |
| 552 | .vendor = PCI_VENDOR_ID_AMD, |
| 553 | .device = PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_HT, |
| 554 | }; |
| 555 | |
| 556 | static const struct pci_driver family10_northbridge __pci_driver = { |
| 557 | .ops = &northbridge_operations, |
| 558 | .vendor = PCI_VENDOR_ID_AMD, |
| 559 | .device = PCI_DEVICE_ID_AMD_10H_NB_HT, |
| 560 | }; |
| 561 | |
| 562 | struct chip_operations northbridge_amd_pi_00630F01_ops = { |
| 563 | CHIP_NAME("AMD FAM15 Northbridge") |
| 564 | .enable_dev = 0, |
| 565 | }; |
| 566 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 567 | static void domain_read_resources(struct device *dev) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 568 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 569 | unsigned int reg; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 570 | |
| 571 | /* Find the already assigned resource pairs */ |
| 572 | get_fx_devs(); |
| 573 | for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { |
| 574 | u32 base, limit; |
| 575 | base = f1_read_config32(reg); |
| 576 | limit = f1_read_config32(reg + 0x04); |
| 577 | /* Is this register allocated? */ |
| 578 | if ((base & 3) != 0) { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 579 | unsigned int nodeid, reg_link; |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 580 | struct device *reg_dev; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 581 | if (reg < 0xc0) { // mmio |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 582 | nodeid = (limit & 0xf) + (base&0x30); |
| 583 | } else { // io |
| 584 | nodeid = (limit & 0xf) + ((base>>4)&0x30); |
| 585 | } |
| 586 | reg_link = (limit >> 4) & 7; |
| 587 | reg_dev = __f0_dev[nodeid]; |
| 588 | if (reg_dev) { |
| 589 | /* Reserve the resource */ |
| 590 | struct resource *res; |
| 591 | res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); |
| 592 | if (res) { |
| 593 | res->flags = 1; |
| 594 | } |
| 595 | } |
| 596 | } |
| 597 | } |
| 598 | /* FIXME: do we need to check extend conf space? |
| 599 | I don't believe that much preset value */ |
| 600 | |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 601 | pci_domain_read_resources(dev); |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 602 | |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 603 | } |
| 604 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 605 | static void domain_enable_resources(struct device *dev) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 606 | { |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 607 | } |
| 608 | |
| 609 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 610 | struct hw_mem_hole_info { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 611 | unsigned int hole_startk; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 612 | int node_id; |
| 613 | }; |
| 614 | static struct hw_mem_hole_info get_hw_mem_hole_info(void) |
| 615 | { |
| 616 | struct hw_mem_hole_info mem_hole; |
| 617 | int i; |
| 618 | mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; |
| 619 | mem_hole.node_id = -1; |
| 620 | for (i = 0; i < node_nums; i++) { |
| 621 | dram_base_mask_t d; |
| 622 | u32 hole; |
| 623 | d = get_dram_base_mask(i); |
| 624 | if (!(d.mask & 1)) continue; // no memory on this node |
| 625 | hole = pci_read_config32(__f1_dev[i], 0xf0); |
| 626 | if (hole & 1) { // we find the hole |
| 627 | mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; |
| 628 | mem_hole.node_id = i; // record the node No with hole |
| 629 | break; // only one hole |
| 630 | } |
| 631 | } |
| 632 | |
| 633 | /* We need to double check if there is special set on base reg and limit reg |
| 634 | * are not continuous instead of hole, it will find out its hole_startk. |
| 635 | */ |
| 636 | if (mem_hole.node_id == -1) { |
| 637 | resource_t limitk_pri = 0; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 638 | for (i = 0; i < node_nums; i++) { |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 639 | dram_base_mask_t d; |
| 640 | resource_t base_k, limit_k; |
| 641 | d = get_dram_base_mask(i); |
| 642 | if (!(d.base & 1)) continue; |
| 643 | base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; |
| 644 | if (base_k > 4 *1024 * 1024) break; // don't need to go to check |
| 645 | if (limitk_pri != base_k) { // we find the hole |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 646 | mem_hole.hole_startk = (unsigned int)limitk_pri; // must be below 4G |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 647 | mem_hole.node_id = i; |
| 648 | break; //only one hole |
| 649 | } |
| 650 | limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; |
| 651 | limitk_pri = limit_k; |
| 652 | } |
| 653 | } |
| 654 | return mem_hole; |
| 655 | } |
| 656 | #endif |
| 657 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 658 | static void domain_set_resources(struct device *dev) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 659 | { |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 660 | unsigned long mmio_basek; |
| 661 | u32 pci_tolm; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 662 | int i, idx; |
| 663 | struct bus *link; |
| 664 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 665 | struct hw_mem_hole_info mem_hole; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 666 | #endif |
| 667 | |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 668 | pci_tolm = 0xffffffffUL; |
| 669 | for (link = dev->link_list; link; link = link->next) { |
| 670 | pci_tolm = find_pci_tolm(link); |
| 671 | } |
| 672 | |
| 673 | // FIXME handle interleaved nodes. If you fix this here, please fix |
| 674 | // amdk8, too. |
| 675 | mmio_basek = pci_tolm >> 10; |
| 676 | /* Round mmio_basek to something the processor can support */ |
| 677 | mmio_basek &= ~((1 << 6) -1); |
| 678 | |
| 679 | // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M |
| 680 | // MMIO hole. If you fix this here, please fix amdk8, too. |
| 681 | /* Round the mmio hole to 64M */ |
| 682 | mmio_basek &= ~((64*1024) - 1); |
| 683 | |
| 684 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 685 | /* if the hw mem hole is already set in raminit stage, here we will compare |
| 686 | * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will |
| 687 | * use hole_basek as mmio_basek and we don't need to reset hole. |
| 688 | * otherwise We reset the hole to the mmio_basek |
| 689 | */ |
| 690 | |
| 691 | mem_hole = get_hw_mem_hole_info(); |
| 692 | |
| 693 | // Use hole_basek as mmio_basek, and we don't need to reset hole anymore |
| 694 | if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { |
| 695 | mmio_basek = mem_hole.hole_startk; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 696 | } |
| 697 | #endif |
| 698 | |
| 699 | idx = 0x10; |
| 700 | for (i = 0; i < node_nums; i++) { |
| 701 | dram_base_mask_t d; |
| 702 | resource_t basek, limitk, sizek; // 4 1T |
| 703 | |
| 704 | d = get_dram_base_mask(i); |
| 705 | |
| 706 | if (!(d.mask & 1)) continue; |
| 707 | basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here |
Elyes HAOUAS | 7db506c | 2016-10-02 11:56:39 +0200 | [diff] [blame] | 708 | limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 709 | |
| 710 | sizek = limitk - basek; |
| 711 | |
| 712 | /* see if we need a hole from 0xa0000 to 0xbffff */ |
| 713 | if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { |
| 714 | ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); |
| 715 | idx += 0x10; |
| 716 | basek = (8*64)+(16*16); |
| 717 | sizek = limitk - ((8*64)+(16*16)); |
| 718 | |
| 719 | } |
| 720 | |
| 721 | //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); |
| 722 | |
| 723 | /* split the region to accommodate pci memory space */ |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 724 | if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 725 | if (basek <= mmio_basek) { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 726 | unsigned int pre_sizek; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 727 | pre_sizek = mmio_basek - basek; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 728 | if (pre_sizek > 0) { |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 729 | ram_resource(dev, (idx | i), basek, pre_sizek); |
| 730 | idx += 0x10; |
| 731 | sizek -= pre_sizek; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 732 | } |
| 733 | basek = mmio_basek; |
| 734 | } |
| 735 | if ((basek + sizek) <= 4*1024*1024) { |
| 736 | sizek = 0; |
| 737 | } |
| 738 | else { |
| 739 | uint64_t topmem2 = bsp_topmem2(); |
| 740 | basek = 4*1024*1024; |
| 741 | sizek = topmem2/1024 - basek; |
| 742 | } |
| 743 | } |
| 744 | |
| 745 | ram_resource(dev, (idx | i), basek, sizek); |
| 746 | idx += 0x10; |
| 747 | printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", |
| 748 | i, mmio_basek, basek, limitk); |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 749 | } |
| 750 | |
Kyösti Mälkki | e87564f | 2017-04-15 20:07:53 +0300 | [diff] [blame] | 751 | add_uma_resource_below_tolm(dev, 7); |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 752 | |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 753 | for (link = dev->link_list; link; link = link->next) { |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 754 | if (link->children) { |
| 755 | assign_resources(link); |
| 756 | } |
| 757 | } |
| 758 | } |
| 759 | |
| 760 | static struct device_operations pci_domain_ops = { |
| 761 | .read_resources = domain_read_resources, |
| 762 | .set_resources = domain_set_resources, |
| 763 | .enable_resources = domain_enable_resources, |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 764 | .scan_bus = pci_domain_scan_bus, |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 765 | }; |
| 766 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 767 | static void sysconf_init(struct device *dev) // first node |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 768 | { |
| 769 | sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 |
| 770 | node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] |
| 771 | } |
| 772 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 773 | static void cpu_bus_scan(struct device *dev) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 774 | { |
| 775 | struct bus *cpu_bus; |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 776 | struct device *dev_mc; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 777 | int i,j; |
| 778 | int coreid_bits; |
| 779 | int core_max = 0; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 780 | unsigned int ApicIdCoreIdSize; |
| 781 | unsigned int core_nums; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 782 | int siblings = 0; |
| 783 | unsigned int family; |
| 784 | u32 modules = 0; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 785 | int ioapic_count = 0; |
| 786 | |
Michał Żygowski | e719288 | 2019-11-23 19:02:19 +0100 | [diff] [blame] | 787 | /* For binaryPI there is no multiprocessor configuration, the number of |
| 788 | * modules will always be 1. */ |
| 789 | modules = 1; |
| 790 | ioapic_count = CONFIG_NUM_OF_IOAPICS; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 791 | |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 792 | dev_mc = pcidev_on_root(DEV_CDB, 0); |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 793 | if (!dev_mc) { |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 794 | printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 795 | die(""); |
| 796 | } |
| 797 | sysconf_init(dev_mc); |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 798 | |
| 799 | /* Get Max Number of cores(MNC) */ |
Kyösti Mälkki | d41feed | 2017-09-24 16:23:57 +0300 | [diff] [blame] | 800 | coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 801 | core_max = 1 << (coreid_bits & 0x000F); //mnc |
| 802 | |
| 803 | ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); |
| 804 | if (ApicIdCoreIdSize) { |
| 805 | core_nums = (1 << ApicIdCoreIdSize) - 1; |
| 806 | } else { |
| 807 | core_nums = 3; //quad core |
| 808 | } |
| 809 | |
| 810 | /* Find which cpus are present */ |
| 811 | cpu_bus = dev->link_list; |
| 812 | for (i = 0; i < node_nums; i++) { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 813 | struct device *cdb_dev; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 814 | unsigned int devn; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 815 | struct bus *pbus; |
| 816 | |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 817 | devn = DEV_CDB + i; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 818 | pbus = dev_mc->bus; |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 819 | |
| 820 | /* Find the cpu's pci device */ |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 821 | cdb_dev = pcidev_on_root(devn, 0); |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 822 | if (!cdb_dev) { |
| 823 | /* If I am probing things in a weird order |
| 824 | * ensure all of the cpu's pci devices are found. |
| 825 | */ |
| 826 | int fn; |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 827 | for (fn = 0; fn <= 5; fn++) { //FBDIMM? |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 828 | cdb_dev = pci_probe_dev(NULL, pbus, |
| 829 | PCI_DEVFN(devn, fn)); |
| 830 | } |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 831 | cdb_dev = pcidev_on_root(devn, 0); |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 832 | } else { |
| 833 | /* Ok, We need to set the links for that device. |
| 834 | * otherwise the device under it will not be scanned |
| 835 | */ |
Martin Roth | d45a347 | 2015-11-26 21:51:03 -0700 | [diff] [blame] | 836 | add_more_links(cdb_dev, 4); |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 837 | } |
| 838 | |
| 839 | family = cpuid_eax(1); |
| 840 | family = (family >> 20) & 0xFF; |
| 841 | if (family == 1) { //f10 |
| 842 | u32 dword; |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 843 | cdb_dev = pcidev_on_root(devn, 3); |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 844 | dword = pci_read_config32(cdb_dev, 0xe8); |
| 845 | siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); |
| 846 | } else if (family == 6) {//f15 |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 847 | cdb_dev = pcidev_on_root(devn, 5); |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 848 | if (cdb_dev && cdb_dev->enabled) { |
| 849 | siblings = pci_read_config32(cdb_dev, 0x84); |
| 850 | siblings &= 0xFF; |
| 851 | } |
| 852 | } else { |
| 853 | siblings = 0; //default one core |
| 854 | } |
| 855 | int enable_node = cdb_dev && cdb_dev->enabled; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 856 | printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 857 | dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); |
| 858 | |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 859 | for (j = 0; j <= siblings; j++) { |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 860 | u32 lapicid_start = 0; |
| 861 | |
| 862 | /* |
Elyes HAOUAS | 38a4f2a9 | 2020-01-07 19:53:36 +0100 | [diff] [blame] | 863 | * APIC ID calculation is tightly coupled with AGESA v5 code. |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 864 | * This calculation MUST match the assignment calculation done |
| 865 | * in LocalApicInitializationAtEarly() function. |
| 866 | * And reference GetLocalApicIdForCore() |
| 867 | * |
Elyes HAOUAS | a5b0bc4 | 2020-02-20 20:04:29 +0100 | [diff] [blame] | 868 | * Apply APIC enumeration rules |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 869 | * For systems with >= 16 APICs, put the IO-APICs at 0..n and |
| 870 | * put the local-APICs at m..z |
| 871 | * |
| 872 | * This is needed because many IO-APIC devices only have 4 bits |
| 873 | * for their APIC id and therefore must reside at 0..15 |
Elyes HAOUAS | 6e8b3c1 | 2016-09-02 19:22:00 +0200 | [diff] [blame] | 874 | */ |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 875 | if ((node_nums * core_max) + ioapic_count >= 0x10) { |
| 876 | lapicid_start = (ioapic_count - 1) / core_max; |
| 877 | lapicid_start = (lapicid_start + 1) * core_max; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 878 | printk(BIOS_SPEW, "lapicid_start = 0x%x ", lapicid_start); |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 879 | } |
| 880 | u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 881 | printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 882 | i, j, apic_id); |
| 883 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 884 | struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 885 | if (cpu) |
| 886 | amd_cpu_topology(cpu, i, j); |
| 887 | } //j |
| 888 | } |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 889 | } |
| 890 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 891 | static void cpu_bus_init(struct device *dev) |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 892 | { |
| 893 | initialize_cpus(dev->link_list); |
| 894 | } |
| 895 | |
| 896 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame^] | 897 | .read_resources = noop_read_resources, |
| 898 | .set_resources = noop_set_resources, |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 899 | .init = cpu_bus_init, |
| 900 | .scan_bus = cpu_bus_scan, |
| 901 | }; |
| 902 | |
| 903 | static void root_complex_enable_dev(struct device *dev) |
| 904 | { |
| 905 | static int done = 0; |
| 906 | |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 907 | if (!done) { |
| 908 | setup_bsp_ramtop(); |
Bruce Griffith | 006364e | 2014-10-22 03:33:49 -0600 | [diff] [blame] | 909 | done = 1; |
| 910 | } |
| 911 | |
| 912 | /* Set the operations if it is a special bus type */ |
| 913 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 914 | dev->ops = &pci_domain_ops; |
| 915 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 916 | dev->ops = &cpu_bus_ops; |
| 917 | } |
| 918 | } |
| 919 | |
| 920 | struct chip_operations northbridge_amd_pi_00630F01_root_complex_ops = { |
| 921 | CHIP_NAME("AMD FAM15 Root Complex") |
| 922 | .enable_dev = root_complex_enable_dev, |
| 923 | }; |
| 924 | |
| 925 | /********************************************************************* |
| 926 | * Change the vendor / device IDs to match the generic VBIOS header. * |
| 927 | *********************************************************************/ |
| 928 | u32 map_oprom_vendev(u32 vendev) |
| 929 | { |
| 930 | u32 new_vendev = vendev; |
| 931 | |
| 932 | if (vendev == 0x10021308) |
| 933 | ; /* Do nothing, this is the HDMI HD Audio device */ |
| 934 | else if ((0x10021300 <= vendev) && (vendev <= 0x1002131F)) { |
| 935 | new_vendev = 0x10021304; |
| 936 | } |
| 937 | |
| 938 | if (vendev != new_vendev) |
| 939 | printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); |
| 940 | |
| 941 | return new_vendev; |
| 942 | } |