blob: 80aaf715afa0b3660f8115e4c568e64d175c00b6 [file] [log] [blame]
Hannah Williams01bc8972016-02-04 20:13:34 -08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
5 * Copyright (C) 2015-2016 Intel Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
Alexandru Gagniuca6339802016-04-05 12:40:24 -070018#define __SIMPLE_DEVICE__
19
Duncan Laurie2e790092016-09-19 12:05:49 -070020#include <arch/acpi.h>
Hannah Williams01bc8972016-02-04 20:13:34 -080021#include <arch/io.h>
22#include <console/console.h>
Shaunak Saha60b46182016-08-02 17:25:13 -070023#include <cbmem.h>
Hannah Williams01bc8972016-02-04 20:13:34 -080024#include <rules.h>
25#include <device/pci_def.h>
Aaron Durbinc2b77792016-07-14 00:26:50 -050026#include <halt.h>
Hannah Williams01bc8972016-02-04 20:13:34 -080027#include <soc/iomap.h>
Alexandru Gagniuca6339802016-04-05 12:40:24 -070028#include <soc/pci_devs.h>
Hannah Williams01bc8972016-02-04 20:13:34 -080029#include <soc/pm.h>
30#include <device/device.h>
31#include <device/pci.h>
Furquan Shaikh2a12e2e2016-07-25 11:48:03 -070032#include <vboot/vboot_common.h>
Duncan Lauriea673d1c2016-09-19 12:02:54 -070033#include "chip.h"
Hannah Williams01bc8972016-02-04 20:13:34 -080034
Alexandru Gagniuca6339802016-04-05 12:40:24 -070035static uintptr_t read_pmc_mmio_bar(void)
36{
Lijian Zhao91086802016-09-06 18:15:29 -070037 return PMC_BAR0;
Alexandru Gagniuca6339802016-04-05 12:40:24 -070038}
Hannah Williams01bc8972016-02-04 20:13:34 -080039
Shaunak Saha9a0c9ac2016-06-27 23:00:15 -070040uintptr_t get_pmc_mmio_bar(void)
41{
42 return read_pmc_mmio_bar();
43}
44
Hannah Williams01bc8972016-02-04 20:13:34 -080045static void print_num_status_bits(int num_bits, uint32_t status,
46 const char * const bit_names[])
47{
48 int i;
49
50 if (!status)
51 return;
52
53 for (i = num_bits - 1; i >= 0; i--) {
54 if (status & (1 << i)) {
55 if (bit_names[i])
56 printk(BIOS_DEBUG, "%s ", bit_names[i]);
57 else
58 printk(BIOS_DEBUG, "BIT%d ", i);
59 }
60 }
61}
62
63static uint32_t print_smi_status(uint32_t smi_sts)
64{
65 static const char * const smi_sts_bits[] = {
Aaron Durbin7929dd02016-06-10 18:01:45 -050066 [BIOS_SMI_STS] = "BIOS",
67 [LEGACY_USB_SMI_STS] = "LEGACY USB",
68 [SLP_SMI_STS] = "SLP_SMI",
69 [APM_SMI_STS] = "APM",
70 [SWSMI_TMR_SMI_STS] = "SWSMI_TMR",
Aaron Durbina554b712016-06-10 18:04:21 -050071 [FAKE_PM1_SMI_STS] = "PM1",
Aaron Durbin7929dd02016-06-10 18:01:45 -050072 [GPIO_SMI_STS]= "GPIO_SMI",
73 [GPIO_UNLOCK_SMI_STS]= "GPIO_UNLOCK_SSMI",
74 [MC_SMI_STS] = "MCSMI",
75 [TCO_SMI_STS] = "TCO",
76 [PERIODIC_SMI_STS] = "PERIODIC",
77 [SERIRQ_SMI_STS] = "SERIRQ",
78 [SMBUS_SMI_STS] = "SMBUS_SMI",
79 [XHCI_SMI_STS] = "XHCI",
80 [HSMBUS_SMI_STS] = "HOST_SMBUS",
81 [SCS_SMI_STS] = "SCS",
82 [PCIE_SMI_STS] = "PCI_EXP_SMI",
83 [SCC2_SMI_STS] = "SCC2",
84 [SPI_SSMI_STS] = "SPI_SSMI",
85 [SPI_SMI_STS] = "SPI",
86 [PMC_OCP_SMI_STS] = "OCP_CSE",
Hannah Williams01bc8972016-02-04 20:13:34 -080087 };
88
89 if (!smi_sts)
90 return 0;
91
92 printk(BIOS_DEBUG, "SMI_STS: ");
93 print_num_status_bits(ARRAY_SIZE(smi_sts_bits), smi_sts, smi_sts_bits);
94 printk(BIOS_DEBUG, "\n");
95
96 return smi_sts;
97}
98
99static uint32_t reset_smi_status(void)
100{
101 uint32_t smi_sts = inl(ACPI_PMIO_BASE + SMI_STS);
102 outl(smi_sts, ACPI_PMIO_BASE + SMI_STS);
103 return smi_sts;
104}
105
106uint32_t clear_smi_status(void)
107{
Aaron Durbina554b712016-06-10 18:04:21 -0500108 uint32_t sts = reset_smi_status();
109
110 /*
111 * Check for power button status if nothing else is indicating an SMI
112 * and SMIs aren't turned into SCIs. Apparently, there is no PM1 status
113 * bit in the SMI status register. That makes things difficult for
114 * determining if the power button caused an SMI.
115 */
116 if (sts == 0 && !(inl(ACPI_PMIO_BASE + PM1_CNT) & SCI_EN)) {
117 uint16_t pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS);
118
119 /* Fake PM1 status bit if power button pressed. */
120 if (pm1_sts & PWRBTN_STS)
121 sts |= (1 << FAKE_PM1_SMI_STS);
122 }
123
124 return print_smi_status(sts);
Hannah Williams01bc8972016-02-04 20:13:34 -0800125}
126
127uint32_t get_smi_en(void)
128{
129 return inl(ACPI_PMIO_BASE + SMI_EN);
130}
131
132void enable_smi(uint32_t mask)
133{
134 uint32_t smi_en = inl(ACPI_PMIO_BASE + SMI_EN);
135 smi_en |= mask;
136 outl(smi_en, ACPI_PMIO_BASE + SMI_EN);
137}
138
139void disable_smi(uint32_t mask)
140{
141 uint32_t smi_en = inl(ACPI_PMIO_BASE + SMI_EN);
142 smi_en &= ~mask;
143 outl(smi_en, ACPI_PMIO_BASE + SMI_EN);
144}
145
146void enable_pm1_control(uint32_t mask)
147{
148 uint32_t pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT);
149 pm1_cnt |= mask;
150 outl(pm1_cnt, ACPI_PMIO_BASE + PM1_CNT);
151}
152
153void disable_pm1_control(uint32_t mask)
154{
155 uint32_t pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT);
156 pm1_cnt &= ~mask;
157 outl(pm1_cnt, ACPI_PMIO_BASE + PM1_CNT);
158}
159
160static uint16_t reset_pm1_status(void)
161{
162 uint16_t pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS);
163 outw(pm1_sts, ACPI_PMIO_BASE + PM1_STS);
164 return pm1_sts;
165}
166
167static uint16_t print_pm1_status(uint16_t pm1_sts)
168{
169 static const char * const pm1_sts_bits[] = {
170 [0] = "TMROF",
171 [5] = "GBL",
172 [8] = "PWRBTN",
173 [10] = "RTC",
174 [11] = "PRBTNOR",
175 [13] = "USB",
176 [14] = "PCIEXPWAK",
177 [15] = "WAK",
178 };
179
180 if (!pm1_sts)
181 return 0;
182
183 printk(BIOS_SPEW, "PM1_STS: ");
184 print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits);
185 printk(BIOS_SPEW, "\n");
186
187 return pm1_sts;
188}
189
190uint16_t clear_pm1_status(void)
191{
192 return print_pm1_status(reset_pm1_status());
193}
194
195void enable_pm1(uint16_t events)
196{
197 outw(events, ACPI_PMIO_BASE + PM1_EN);
198}
199
200static uint32_t print_tco_status(uint32_t tco_sts)
201{
202 static const char * const tco_sts_bits[] = {
203 [3] = "TIMEOUT",
204 [17] = "SECOND_TO",
205 };
206
207 if (!tco_sts)
208 return 0;
209
210 printk(BIOS_DEBUG, "TCO_STS: ");
211 print_num_status_bits(ARRAY_SIZE(tco_sts_bits), tco_sts, tco_sts_bits);
212 printk(BIOS_DEBUG, "\n");
213
214 return tco_sts;
215}
216
217static uint32_t reset_tco_status(void)
218{
219 uint32_t tco_sts = inl(ACPI_PMIO_BASE + TCO_STS);
220 uint32_t tco_en = inl(ACPI_PMIO_BASE + TCO1_CNT);
221
222 outl(tco_sts, ACPI_PMIO_BASE + TCO_STS);
223 return tco_sts & tco_en;
224}
225
226uint32_t clear_tco_status(void)
227{
228 return print_tco_status(reset_tco_status());
229}
230
231void enable_gpe(uint32_t mask)
232{
233 uint32_t gpe0a_en = inl(ACPI_PMIO_BASE + GPE0_EN(0));
234 gpe0a_en |= mask;
235 outl(gpe0a_en, ACPI_PMIO_BASE + GPE0_EN(0));
236}
237
238void disable_gpe(uint32_t mask)
239{
240 uint32_t gpe0a_en = inl(ACPI_PMIO_BASE + GPE0_EN(0));
241 gpe0a_en &= ~mask;
242 outl(gpe0a_en, ACPI_PMIO_BASE + GPE0_EN(0));
243}
244
245void disable_all_gpe(void)
246{
247 disable_gpe(~0);
248}
249
Shaunak Sahad6bb5492016-08-22 21:55:23 -0700250/* Clear the gpio gpe0 status bits in ACPI registers */
251void clear_gpi_gpe_sts(void)
252{
253 int i;
254
255 for (i = 1; i < GPE0_REG_MAX; i++) {
256 uint32_t gpe_sts = inl(ACPI_PMIO_BASE + GPE0_STS(i));
257 outl(gpe_sts, ACPI_PMIO_BASE + GPE0_STS(i));
258 }
259}
Hannah Williams01bc8972016-02-04 20:13:34 -0800260
261static uint32_t reset_gpe_status(void)
262{
263 uint32_t gpe_sts = inl(ACPI_PMIO_BASE + GPE0_STS(0));
264 outl(gpe_sts, ACPI_PMIO_BASE + GPE0_STS(0));
265 return gpe_sts;
266}
267
268static uint32_t print_gpe_sts(uint32_t gpe_sts)
269{
270 static const char * const gpe_sts_bits[] = {
271 [0] = "PCIE_SCI",
272 [2] = "SWGPE",
273 [3] = "PCIE_WAKE0",
274 [4] = "PUNIT",
275 [6] = "PCIE_WAKE1",
276 [7] = "PCIE_WAKE2",
277 [8] = "PCIE_WAKE3",
278 [9] = "PCI_EXP",
279 [10] = "BATLOW",
280 [11] = "CSE_PME",
281 [12] = "XDCI_PME",
282 [13] = "XHCI_PME",
283 [14] = "AVS_PME",
284 [15] = "GPIO_TIER1_SCI",
285 [16] = "SMB_WAK",
286 [17] = "SATA_PME",
287 };
288
289 if (!gpe_sts)
290 return gpe_sts;
291
292 printk(BIOS_DEBUG, "GPE0a_STS: ");
293 print_num_status_bits(ARRAY_SIZE(gpe_sts_bits), gpe_sts, gpe_sts_bits);
294 printk(BIOS_DEBUG, "\n");
295
296 return gpe_sts;
297}
298
299uint32_t clear_gpe_status(void)
300{
301 return print_gpe_sts(reset_gpe_status());
302}
303
Duncan Laurie2e790092016-09-19 12:05:49 -0700304/* Read and clear GPE status (defined in arch/acpi.h) */
305int acpi_get_gpe(int gpe)
306{
307 int bank;
308 uint32_t mask, sts;
309
310 if (gpe < 0 || gpe > GPE0_DW3_31)
311 return -1;
312
313 bank = gpe / 32;
314 mask = 1 << (gpe % 32);
315
316 sts = inl(ACPI_PMIO_BASE + GPE0_STS(bank));
317 if (sts & mask) {
318 outl(mask, ACPI_PMIO_BASE + GPE0_STS(bank));
319 return 1;
320 }
321 return 0;
322}
323
Hannah Williams01bc8972016-02-04 20:13:34 -0800324void clear_pmc_status(void)
325{
326 uint32_t prsts;
327 uint32_t gen_pmcon1;
Alexandru Gagniuca6339802016-04-05 12:40:24 -0700328 uintptr_t pmc_bar0 = read_pmc_mmio_bar();
Hannah Williams01bc8972016-02-04 20:13:34 -0800329
Alexandru Gagniuca6339802016-04-05 12:40:24 -0700330 prsts = read32((void *)(pmc_bar0 + PRSTS));
331 gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1));
Hannah Williams01bc8972016-02-04 20:13:34 -0800332
333 /* Clear the status bits. The RPS field is cleared on a 0 write. */
Alexandru Gagniuca6339802016-04-05 12:40:24 -0700334 write32((void *)(pmc_bar0 + GEN_PMCON1), gen_pmcon1 & ~RPS);
335 write32((void *)(pmc_bar0 + PRSTS), prsts);
Hannah Williams01bc8972016-02-04 20:13:34 -0800336}
337
338
339/* Return 0, 3, or 5 to indicate the previous sleep state. */
340int chipset_prev_sleep_state(struct chipset_power_state *ps)
341{
342 /* Default to S0. */
Aaron Durbined35b7c2016-07-13 23:17:38 -0500343 int prev_sleep_state = ACPI_S0;
Hannah Williams01bc8972016-02-04 20:13:34 -0800344
345 if (ps->pm1_sts & WAK_STS) {
Aaron Durbined35b7c2016-07-13 23:17:38 -0500346 switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
347 case ACPI_S3:
348 if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
349 prev_sleep_state = ACPI_S3;
Hannah Williams01bc8972016-02-04 20:13:34 -0800350 break;
Aaron Durbined35b7c2016-07-13 23:17:38 -0500351 case ACPI_S5:
352 prev_sleep_state = ACPI_S5;
Hannah Williams01bc8972016-02-04 20:13:34 -0800353 break;
354 }
Hannah Williams5992afa2016-06-23 09:50:28 -0700355
356 /* Clear SLP_TYP. */
357 outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_PMIO_BASE + PM1_CNT);
Hannah Williams01bc8972016-02-04 20:13:34 -0800358 }
359 return prev_sleep_state;
360}
361
Shaunak Saha60b46182016-08-02 17:25:13 -0700362/*
363 * This function re-writes the gpe0 register values in power state
364 * cbmem variable. After system wakes from sleep state internal PMC logic
365 * writes default values in GPE_CFG register which gives a wrong offset to
366 * calculate the wake reason. So we need to set it again to the routing
367 * table as per the devicetree.
368 */
369void fixup_power_state(void)
370{
371 int i;
372 struct chipset_power_state *ps;
373
374 ps = cbmem_find(CBMEM_ID_POWER_STATE);
375 if (ps == NULL)
376 return;
377
378 for (i = 0; i < GPE0_REG_MAX; i++) {
379 ps->gpe0_sts[i] = inl(ACPI_PMIO_BASE + GPE0_STS(i));
380 ps->gpe0_en[i] = inl(ACPI_PMIO_BASE + GPE0_EN(i));
381 printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n",
382 i, ps->gpe0_sts[i], i, ps->gpe0_en[i]);
383 }
384}
385
Hannah Williams01bc8972016-02-04 20:13:34 -0800386/* returns prev_sleep_state */
387int fill_power_state(struct chipset_power_state *ps)
388{
389 int i;
Alexandru Gagniuca6339802016-04-05 12:40:24 -0700390 uintptr_t pmc_bar0 = read_pmc_mmio_bar();
391
Hannah Williams01bc8972016-02-04 20:13:34 -0800392 ps->pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS);
393 ps->pm1_en = inw(ACPI_PMIO_BASE + PM1_EN);
394 ps->pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT);
395 ps->tco_sts = inl(ACPI_PMIO_BASE + TCO_STS);
Alexandru Gagniuca6339802016-04-05 12:40:24 -0700396 ps->prsts = read32((void *)(pmc_bar0 + PRSTS));
397 ps->gen_pmcon1 =read32((void *)(pmc_bar0 + GEN_PMCON1));
398 ps->gen_pmcon2 = read32((void *)(pmc_bar0 + GEN_PMCON2));
399 ps->gen_pmcon3 = read32((void *)(pmc_bar0 + GEN_PMCON3));
Hannah Williams01bc8972016-02-04 20:13:34 -0800400
401 ps->prev_sleep_state = chipset_prev_sleep_state(ps);
402
403 printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
404 ps->pm1_sts, ps->pm1_en, ps->pm1_cnt);
405 printk(BIOS_DEBUG, "prsts: %08x tco_sts: %08x\n",
406 ps->prsts, ps->tco_sts);
407 printk(BIOS_DEBUG,
408 "gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n",
409 ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
410 printk(BIOS_DEBUG, "smi_en: %08x smi_sts: %08x\n",
411 inl(ACPI_PMIO_BASE + SMI_EN), inl(ACPI_PMIO_BASE + SMI_STS));
412 for (i=0; i < GPE0_REG_MAX; i++) {
413 ps->gpe0_sts[i] = inl(ACPI_PMIO_BASE + GPE0_STS(i));
414 ps->gpe0_en[i] = inl(ACPI_PMIO_BASE + GPE0_EN(i));
415 printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n",
416 i, ps->gpe0_sts[i], i, ps->gpe0_en[i]);
417 }
418 printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
419 return ps->prev_sleep_state;
420}
Aaron Durbinbef75e72016-05-26 11:00:44 -0500421
422int vboot_platform_is_resuming(void)
423{
Aaron Durbinbef75e72016-05-26 11:00:44 -0500424 if (!(inw(ACPI_PMIO_BASE + PM1_STS) & WAK_STS))
425 return 0;
426
Aaron Durbined35b7c2016-07-13 23:17:38 -0500427 return acpi_sleep_from_pm1(inl(ACPI_PMIO_BASE + PM1_CNT)) == ACPI_S3;
Aaron Durbinbef75e72016-05-26 11:00:44 -0500428}
Andrey Petrov0f593c22016-06-17 15:30:13 -0700429
430/*
431 * If possible, lock 0xcf9. Once the register is locked, it can't be changed.
432 * This lock is reset on cold boot, hard reset, soft reset and Sx.
433 */
434void global_reset_lock(void)
435{
436 uintptr_t etr = read_pmc_mmio_bar() + ETR;
437 uint32_t reg;
438
439 reg = read32((void *)etr);
440 if (reg & CF9_LOCK)
441 return;
442 reg |= CF9_LOCK;
443 write32((void *)etr, reg);
444}
445
446/*
447 * Enable or disable global reset. If global reset is enabled, hard reset and
448 * soft reset will trigger global reset, where both host and TXE are reset.
449 * This is cleared on cold boot, hard reset, soft reset and Sx.
450 */
451void global_reset_enable(bool enable)
452{
453 uintptr_t etr = read_pmc_mmio_bar() + ETR;
454 uint32_t reg;
455
456 reg = read32((void *)etr);
457 reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST;
458 write32((void *)etr, reg);
459}
Furquan Shaikh4c1cb422016-06-23 14:00:05 -0700460
461/*
462 * The PM1 control is set to S5 when vboot requests a reboot because the power
463 * state code above may not have collected its data yet. Therefore, set it to
464 * S5 when vboot requests a reboot. That's necessary if vboot fails in the
465 * resume path and requests a reboot. This prevents a reboot loop where the
466 * error is continually hit on the failing vboot resume path.
467 */
468void vboot_platform_prepare_reboot(void)
469{
470 const uint16_t port = ACPI_PMIO_BASE + PM1_CNT;
471 outl((inl(port) & ~(SLP_TYP)) | (SLP_TYP_S5 << SLP_TYP_SHIFT), port);
472}
Aaron Durbinc2b77792016-07-14 00:26:50 -0500473
474void poweroff(void)
475{
476 enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
Furquan Shaikh3828e552016-08-18 21:31:50 -0700477
478 /*
479 * Setting SLP_TYP_S5 in PM1 triggers SLP_SMI, which is handled by SMM
480 * to transition to S5 state. If halt is called in SMM, then it prevents
481 * the SMI handler from being triggered and system never enters S5.
482 */
483 if (!ENV_SMM)
484 halt();
Aaron Durbinc2b77792016-07-14 00:26:50 -0500485}
Duncan Lauriea673d1c2016-09-19 12:02:54 -0700486
487void pmc_gpe_init(void)
488{
489 uint32_t gpio_cfg = 0;
490 uint32_t gpio_cfg_reg;
491 uint8_t dw1, dw2, dw3;
492 ROMSTAGE_CONST struct soc_intel_apollolake_config *config;
493
494 /* Look up the device in devicetree */
495 ROMSTAGE_CONST struct device *dev = dev_find_slot(0, NB_DEVFN);
496 if (!dev || !dev->chip_info) {
497 printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
498 return;
499 }
500 config = dev->chip_info;
501
502 uintptr_t pmc_bar = get_pmc_mmio_bar();
503
504 const uint32_t gpio_cfg_mask =
505 (GPE0_DWX_MASK << GPE0_DW1_SHIFT) |
506 (GPE0_DWX_MASK << GPE0_DW2_SHIFT) |
507 (GPE0_DWX_MASK << GPE0_DW3_SHIFT);
508
509 /* Assign to local variable */
510 dw1 = config->gpe0_dw1;
511 dw2 = config->gpe0_dw2;
512 dw3 = config->gpe0_dw3;
513
514 /* Making sure that bad values don't bleed into the other fields */
515 dw1 &= GPE0_DWX_MASK;
516 dw2 &= GPE0_DWX_MASK;
517 dw3 &= GPE0_DWX_MASK;
518
519 /* Route the GPIOs to the GPE0 block. Determine that all values
520 * are different, and if they aren't use the reset values.
521 * DW0 is reserved/unused */
522 if (dw1 == dw2 || dw2 == dw3) {
523 printk(BIOS_INFO, "PMC: Using default GPE route.\n");
524 gpio_cfg = read32((void *)pmc_bar + GPIO_GPE_CFG);
525
526 dw1 = (gpio_cfg >> GPE0_DW1_SHIFT) & GPE0_DWX_MASK;
527 dw2 = (gpio_cfg >> GPE0_DW2_SHIFT) & GPE0_DWX_MASK;
528 dw3 = (gpio_cfg >> GPE0_DW3_SHIFT) & GPE0_DWX_MASK;
529 } else {
530 gpio_cfg |= (uint32_t)dw1 << GPE0_DW1_SHIFT;
531 gpio_cfg |= (uint32_t)dw2 << GPE0_DW2_SHIFT;
532 gpio_cfg |= (uint32_t)dw3 << GPE0_DW3_SHIFT;
533 }
534
535 gpio_cfg_reg = read32((void *)pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask;
536 gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask;
537
538 write32((void *)pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg);
539
540 /* Set the routes in the GPIO communities as well. */
541 gpio_route_gpe(dw1, dw2, dw3);
542}