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review.coreboot.org / coreboot / 2efc8808b8bfaee0a0e8f3ee387ecd9a3f049705 / . / src / northbridge / intel / gm45 / acpi.c
blob: da9bfa8f90b2bc9a54a309b06f772cba0407e6e6 [file] [log] [blame]
Patrick Georgi2efc8802012-11-06 11:03:53 +0100[diff] [blame^]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
19 * MA 02110-1301 USA
20 */
21
22#include <types.h>
23#include <string.h>
24#include <console/console.h>
25#include <arch/acpi.h>
26#include <arch/acpigen.h>
27#include <device/device.h>
28#include <device/pci.h>
29#include <device/pci_ids.h>
30#include "gm45.h"
31
32unsigned long acpi_fill_mcfg(unsigned long current)
33{
34 device_t dev;
35 u32 pciexbar = 0;
36 u32 pciexbar_reg;
37 int max_buses;
38
39 dev = dev_find_device(0x8086, 0x2a40, 0);
40 if (!dev)
41 return current;
42
43 pciexbar_reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO);
44
45 // MMCFG not supported or not enabled.
46 if (!(pciexbar_reg & (1 << 0)))
47 return current;
48
49 switch ((pciexbar_reg >> 1) & 3) {
50 case 0: // 256MB
51 pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
52 max_buses = 256;
53 break;
54 case 1: // 128M
55 pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
56 max_buses = 128;
57 break;
58 case 2: // 64M
59 pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
60 max_buses = 64;
61 break;
62 default: // RSVD
63 return current;
64 }
65
66 if (!pciexbar)
67 return current;
68
69 current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
70 pciexbar, 0x0, 0x0, max_buses - 1);
71
72 return current;
73}
74
75unsigned long acpi_fill_dmar(unsigned long current)
76{
77 int me_active = (dev_find_slot(0, PCI_DEVFN(3, 0)) != NULL);
78 int stepping = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), PCI_CLASS_REVISION);
79
80 unsigned long tmp = current;
81 current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1);
82 current += acpi_create_dmar_drhd_ds_pci(current, 0, 0x1b, 0);
83 acpi_dmar_drhd_fixup(tmp, current);
84
85 if (stepping != STEPPING_B2) {
86 tmp = current;
87 current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE2);
88 current += acpi_create_dmar_drhd_ds_pci(current, 0, 0x2, 0);
89 current += acpi_create_dmar_drhd_ds_pci(current, 0, 0x2, 1);
90 acpi_dmar_drhd_fixup(tmp, current);
91 }
92
93 if (me_active) {
94 tmp = current;
95 current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE3);
96 current += acpi_create_dmar_drhd_ds_pci(current, 0, 0x3, 0);
97 current += acpi_create_dmar_drhd_ds_pci(current, 0, 0x3, 1);
98 current += acpi_create_dmar_drhd_ds_pci(current, 0, 0x3, 2);
99 current += acpi_create_dmar_drhd_ds_pci(current, 0, 0x3, 3);
100 acpi_dmar_drhd_fixup(tmp, current);
101 }
102
103 current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE4);
104
105 /* TODO: reserve GTT for 0.2.0 and 0.2.1? */
106 return current;
107}