blob: 22ac2027d9c9a48c37097b2e9ff709391e00e2cd [file] [log] [blame]
Corey Osgood33d1af372007-05-09 08:11:52 +00001/*
Stefan Reinauer7e61e452008-01-18 10:35:56 +00002 * This file is part of the coreboot project.
Corey Osgood33d1af372007-05-09 08:11:52 +00003 *
4 * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
Richard Smith924f92f2006-07-29 17:40:36 +000021#define ASSEMBLY 1
22
23#include <stdint.h>
24#include <device/pci_def.h>
25#include <arch/io.h>
26#include <device/pnp_def.h>
27#include <arch/romcc_io.h>
28#include <arch/hlt.h>
Carl-Daniel Hailfinger2ee67792008-10-01 12:52:52 +000029#include <stdlib.h>
Richard Smith924f92f2006-07-29 17:40:36 +000030#include "pc80/serial.c"
31#include "arch/i386/lib/console.c"
32#include "ram/ramtest.c"
Stefan Reinauerac4ca2b2006-08-04 08:58:17 +000033#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
Richard Smith924f92f2006-07-29 17:40:36 +000034#include "northbridge/intel/i440bx/raminit.h"
Uwe Hermann113c2012007-10-30 23:57:59 +000035#include "mainboard/asus/mew-vm/debug.c" /* FIXME */
Uwe Hermann8c1c1c02007-10-16 00:13:59 +000036#include "pc80/udelay_io.c"
37#include "lib/delay.c"
Richard Smith924f92f2006-07-29 17:40:36 +000038#include "cpu/x86/mtrr/earlymtrr.c"
39#include "cpu/x86/bist.h"
Uwe Hermann113c2012007-10-30 23:57:59 +000040#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
Richard Smith924f92f2006-07-29 17:40:36 +000041
42#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
43
Uwe Hermann8c1c1c02007-10-16 00:13:59 +000044static inline int spd_read_byte(unsigned int device, unsigned int address)
Richard Smith924f92f2006-07-29 17:40:36 +000045{
Uwe Hermann4c0d39f2007-05-15 10:26:16 +000046 return smbus_read_byte(device, address);
Richard Smith924f92f2006-07-29 17:40:36 +000047}
48
Richard Smith924f92f2006-07-29 17:40:36 +000049#include "northbridge/intel/i440bx/raminit.c"
50#include "northbridge/intel/i440bx/debug.c"
51#include "sdram/generic_sdram.c"
52
53static void main(unsigned long bist)
54{
Corey Osgood33d1af372007-05-09 08:11:52 +000055 static const struct mem_controller memctrl[] = {
Richard Smith924f92f2006-07-29 17:40:36 +000056 {
Uwe Hermann8c1c1c02007-10-16 00:13:59 +000057 .d0 = PCI_DEV(0, 0, 0),
58 .channel0 = {0x50, 0x51, 0x52, 0x53},
59 }
Richard Smith924f92f2006-07-29 17:40:36 +000060 };
Uwe Hermann8c1c1c02007-10-16 00:13:59 +000061
62 if (bist == 0)
Richard Smith924f92f2006-07-29 17:40:36 +000063 early_mtrr_init();
Uwe Hermann8c1c1c02007-10-16 00:13:59 +000064
Richard Smith924f92f2006-07-29 17:40:36 +000065 w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE);
66 uart_init();
67 console_init();
Richard Smith924f92f2006-07-29 17:40:36 +000068 report_bist_failure(bist);
Corey Osgood33d1af372007-05-09 08:11:52 +000069 enable_smbus();
Uwe Hermann113c2012007-10-30 23:57:59 +000070 /* dump_spd_registers(&memctrl[0]); */
Carl-Daniel Hailfinger2ee67792008-10-01 12:52:52 +000071 sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
Uwe Hermann113c2012007-10-30 23:57:59 +000072 /* ram_check(0, 640 * 1024); */
Richard Smith924f92f2006-07-29 17:40:36 +000073}