Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; version 2 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <stdint.h> |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 16 | #include <cpu/x86/lapic.h> |
Kyösti Mälkki | 6722f8d | 2014-06-16 09:14:49 +0300 | [diff] [blame] | 17 | #include <arch/acpi.h> |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 18 | #include <console/console.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 19 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 20 | #include <northbridge/intel/sandybridge/raminit.h> |
Vladimir Serbinenko | f004b6b | 2016-02-10 02:42:16 +0100 | [diff] [blame] | 21 | #include <northbridge/intel/sandybridge/raminit_native.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 22 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 23 | #include <southbridge/intel/common/gpio.h> |
Kyösti Mälkki | 926a8d1 | 2014-04-27 22:17:22 +0300 | [diff] [blame] | 24 | #include <bootmode.h> |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 25 | #include <ec/quanta/it8518/ec.h> |
| 26 | #include "ec.h" |
| 27 | #include "onboard.h" |
| 28 | |
Arthur Heymans | 9c53834 | 2019-11-12 16:42:33 +0100 | [diff] [blame] | 29 | void mainboard_late_rcba_config(void) |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 30 | { |
Kyösti Mälkki | 6f49906 | 2015-06-06 11:52:24 +0300 | [diff] [blame] | 31 | /* |
| 32 | * GFX INTA -> PIRQA (MSI) |
| 33 | * D20IP_XHCI XHCI INTA -> PIRQD (MSI) |
| 34 | * D26IP_E2P EHCI #2 INTA -> PIRQF |
| 35 | * D27IP_ZIP HDA INTA -> PIRQA (MSI) |
| 36 | * D28IP_P2IP WLAN INTA -> PIRQD |
| 37 | * D28IP_P3IP Card Reader INTB -> PIRQE |
| 38 | * D28IP_P6IP LAN INTC -> PIRQB |
| 39 | * D29IP_E1P EHCI #1 INTA -> PIRQD |
| 40 | * D31IP_SIP SATA INTA -> PIRQB (MSI) |
| 41 | * D31IP_SMIP SMBUS INTB -> PIRQH |
| 42 | */ |
| 43 | |
| 44 | /* Device interrupt pin register (board specific) */ |
| 45 | RCBA32(D31IP) = (NOINT << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 46 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 47 | RCBA32(D30IP) = (NOINT << D30IP_PIP); |
| 48 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 49 | RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) | |
| 50 | (INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) | |
| 51 | (NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) | |
| 52 | (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); |
| 53 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 54 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 55 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 56 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 57 | RCBA32(D20IP) = (INTA << D20IP_XHCIIP); |
| 58 | |
| 59 | /* Device interrupt route registers */ |
| 60 | DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); |
| 61 | DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); |
| 62 | DIR_ROUTE(D28IR, PIRQD, PIRQE, PIRQB, PIRQC); |
| 63 | DIR_ROUTE(D27IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 64 | DIR_ROUTE(D26IR, PIRQF, PIRQB, PIRQC, PIRQD); |
| 65 | DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 66 | DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 67 | DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG); |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 68 | } |
| 69 | |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 70 | /* |
| 71 | * The Stout EC needs to be reset to RW mode. It is important that |
| 72 | * the RTC_PWR_STS is not set until ramstage EC init. |
| 73 | */ |
| 74 | static void early_ec_init(void) |
| 75 | { |
| 76 | u8 ec_status = ec_read(EC_STATUS_REG); |
Furquan Shaikh | 0325dc6 | 2016-07-25 13:02:36 -0700 | [diff] [blame] | 77 | int rec_mode = get_recovery_mode_switch(); |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 78 | |
| 79 | if (((ec_status & 0x3) == EC_IN_RO_MODE) || |
| 80 | ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)) { |
| 81 | |
| 82 | printk(BIOS_DEBUG, "EC Cold Boot Detected\n"); |
| 83 | if (!rec_mode) { |
| 84 | /* |
| 85 | * Tell EC to exit RO mode |
| 86 | */ |
| 87 | printk(BIOS_DEBUG, "EC will exit RO mode and boot normally\n"); |
| 88 | ec_write_cmd(EC_CMD_EXIT_BOOT_BLOCK); |
| 89 | die("wait for ec to reset"); |
| 90 | } |
| 91 | } else { |
| 92 | printk(BIOS_DEBUG, "EC Warm Boot Detected\n"); |
| 93 | ec_write_cmd(EC_CMD_WARM_RESET); |
| 94 | } |
| 95 | } |
| 96 | |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 97 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
Vladimir Serbinenko | f004b6b | 2016-02-10 02:42:16 +0100 | [diff] [blame] | 98 | { |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 99 | read_spd(&spd[0], 0x50, id_only); |
| 100 | read_spd(&spd[2], 0x52, id_only); |
Vladimir Serbinenko | f004b6b | 2016-02-10 02:42:16 +0100 | [diff] [blame] | 101 | } |
| 102 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 103 | void mainboard_fill_pei_data(struct pei_data *pei_data) |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 104 | { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 105 | struct pei_data pei_data_template = { |
Edward O'Callaghan | 77896c1 | 2014-10-28 10:03:47 +1100 | [diff] [blame] | 106 | .pei_version = PEI_VERSION, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 107 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 108 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
Edward O'Callaghan | 77896c1 | 2014-10-28 10:03:47 +1100 | [diff] [blame] | 109 | .epbar = DEFAULT_EPBAR, |
| 110 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 111 | .smbusbar = SMBUS_IO_BASE, |
| 112 | .wdbbar = 0x4000000, |
| 113 | .wdbsize = 0x1000, |
| 114 | .hpet_address = CONFIG_HPET_ADDRESS, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 115 | .rcba = (uintptr_t)DEFAULT_RCBABASE, |
Edward O'Callaghan | 77896c1 | 2014-10-28 10:03:47 +1100 | [diff] [blame] | 116 | .pmbase = DEFAULT_PMBASE, |
| 117 | .gpiobase = DEFAULT_GPIOBASE, |
| 118 | .thermalbase = 0xfed08000, |
| 119 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 120 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 121 | .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, |
| 122 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 123 | .ec_present = 1, |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 124 | // 0 = leave channel enabled |
| 125 | // 1 = disable dimm 0 on channel |
| 126 | // 2 = disable dimm 1 on channel |
| 127 | // 3 = disable dimm 0+1 on channel |
Edward O'Callaghan | 77896c1 | 2014-10-28 10:03:47 +1100 | [diff] [blame] | 128 | .dimm_channel0_disabled = 2, |
| 129 | .dimm_channel1_disabled = 2, |
| 130 | .max_ddr3_freq = 1600, |
| 131 | .usb_port_config = { |
Elyes HAOUAS | 44f558e | 2020-02-24 13:26:04 +0100 | [diff] [blame] | 132 | /* enabled USB oc pin length */ |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 133 | { 1, 0, 0x0040 }, /* P0: USB 3.0 1 (OC0) */ |
| 134 | { 1, 0, 0x0040 }, /* P1: USB 3.0 2 (OC0) */ |
| 135 | { 0, 1, 0x0000 }, /* P2: Empty */ |
| 136 | { 1, 1, 0x0040 }, /* P3: Camera (no OC) */ |
| 137 | { 1, 1, 0x0040 }, /* P4: WLAN (no OC) */ |
| 138 | { 1, 1, 0x0040 }, /* P5: WWAN (no OC) */ |
| 139 | { 0, 1, 0x0000 }, /* P6: Empty */ |
| 140 | { 0, 1, 0x0000 }, /* P7: Empty */ |
| 141 | { 0, 5, 0x0000 }, /* P8: Empty */ |
| 142 | { 1, 4, 0x0040 }, /* P9: USB 2.0 (AUO4) (OC4) */ |
| 143 | { 0, 5, 0x0000 }, /* P10: Empty */ |
| 144 | { 0, 5, 0x0000 }, /* P11: Empty */ |
| 145 | { 0, 5, 0x0000 }, /* P12: Empty */ |
| 146 | { 1, 5, 0x0040 }, /* P13: Bluetooth (no OC) */ |
| 147 | }, |
Edward O'Callaghan | 77896c1 | 2014-10-28 10:03:47 +1100 | [diff] [blame] | 148 | .usb3 = { |
| 149 | .mode = XHCI_MODE, |
| 150 | .hs_port_switch_mask = XHCI_PORTS, |
| 151 | .preboot_support = XHCI_PREBOOT, |
| 152 | .xhci_streams = XHCI_STREAMS, |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 153 | }, |
| 154 | }; |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 155 | *pei_data = pei_data_template; |
| 156 | } |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 157 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 158 | void mainboard_early_init(int s3resume) |
| 159 | { |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 160 | /* Do ec reset as early as possible, but skip it on S3 resume */ |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 161 | if (!s3resume) { |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 162 | early_ec_init(); |
Stefan Reinauer | b7ecf6d | 2013-03-13 17:13:32 -0700 | [diff] [blame] | 163 | } |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 164 | } |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 165 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 166 | int mainboard_should_reset_usb(int s3resume) |
| 167 | { |
| 168 | return !s3resume; |
| 169 | } |
| 170 | |
Vladimir Serbinenko | f004b6b | 2016-02-10 02:42:16 +0100 | [diff] [blame] | 171 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
Elyes HAOUAS | 44f558e | 2020-02-24 13:26:04 +0100 | [diff] [blame] | 172 | /* enabled USB oc pin length */ |
Elyes HAOUAS | 48a0129 | 2016-09-29 18:57:56 +0200 | [diff] [blame] | 173 | {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */ |
| 174 | {1, 0, 0}, /* P1: USB 3.0 2 (OC0) */ |
| 175 | {0, 0, 0}, /* P2: Empty */ |
| 176 | {1, 0, -1}, /* P3: Camera (no OC) */ |
| 177 | {1, 0, -1}, /* P4: WLAN (no OC) */ |
| 178 | {1, 0, -1}, /* P5: WWAN (no OC) */ |
| 179 | {0, 0, 0}, /* P6: Empty */ |
| 180 | {0, 0, 0}, /* P7: Empty */ |
| 181 | {0, 0, 0}, /* P8: Empty */ |
| 182 | {1, 0, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ |
| 183 | {0, 0, 0}, /* P10: Empty */ |
| 184 | {0, 0, 0}, /* P11: Empty */ |
| 185 | {0, 0, 0}, /* P12: Empty */ |
| 186 | {1, 0, -1}, /* P13: Bluetooth (no OC) */ |
Vladimir Serbinenko | f004b6b | 2016-02-10 02:42:16 +0100 | [diff] [blame] | 187 | }; |