blob: dcb14fa6688b32f875c1f0f458ccae3c8ca95814 [file] [log] [blame]
Frans Hendriks2e1fea42018-11-26 10:33:00 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
5 * Copyright (C) 2018 Eltan B.V.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <arch/io.h>
19#include <device/device.h>
20#include <device/pnp.h>
21#include <superio/conf_mode.h>
22#include <console/console.h>
23#include <string.h>
24#include <pc80/keyboard.h>
25#include "ast2400.h"
26
27static void ast2400_init(struct device *dev)
28{
29 if (!dev->enabled)
30 return;
31
32 switch (dev->path.pnp.device) {
33 case AST2400_KBC:
34 pc_keyboard_init(NO_AUX_DEVICE);
35 break;
36 }
37}
38
39static struct device_operations ops = {
40 .read_resources = pnp_read_resources,
41 .set_resources = pnp_set_resources,
42 .enable_resources = pnp_enable_resources,
43 .enable = pnp_enable,
44 .init = ast2400_init,
45 .ops_pnp_mode = &pnp_conf_mode_a5a5_aa,
46};
47
48static struct pnp_info pnp_dev_info[] = {
49 { NULL, AST2400_SUART1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, },
50 { NULL, AST2400_SUART2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, },
51 { NULL, AST2400_SWAK, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3
52 | PNP_IRQ0, 0xfff8, 0xfff8, 0xfff8, 0xfff8, },
53 { NULL, AST2400_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1
54 | PNP_MSC0, 0xffff, 0xffff, },
55 { NULL, AST2400_GPIO, PNP_IRQ0, }, // GPIO LDN has no IO Region
56 { NULL, AST2400_SUART3, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, },
57 { NULL, AST2400_SUART4, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, },
58 { NULL, AST2400_ILPC2AHB, PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2
59 | PNP_MSC3 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7
60 | PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB | PNP_MSCC
61 | PNP_MSCD | PNP_MSCE, },
62 { NULL, AST2400_MAILBOX, PNP_IO0 | PNP_IRQ0, 0xfffe, },
63};
64
65static void enable_dev(struct device *dev)
66{
67 pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info),
68 pnp_dev_info);
69}
70
71struct chip_operations superio_aspeed_ast2400_ops = {
72 CHIP_NAME("ASpeed AST2400 Super I/O")
73 .enable_dev = enable_dev,
74};