blob: 28d3d1b24d8a4163d505183681bd0b54852de05a [file] [log] [blame]
Nick Vaccaro2dd7b6b2018-08-09 16:18:02 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2018 Google Inc.
5 * Copyright (C) 2018 Intel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <baseboard/variants.h>
18#include <chip.h>
19#include <device/device.h>
20#include <device/pci_ids.h>
21#include <device/pci_ops.h>
22
23/* PL2 limit in watts for AML and KBL */
24#define PL2_AML 18
25#define PL2_KBL 15
26
27static uint32_t get_pl2(void)
28{
29 uint16_t id;
30 id = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID);
31 /* Assume we only have KLB-Y and AML-Y SKUs */
32 if (id == PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM)
33 return PL2_KBL;
34
35 return PL2_AML;
36}
37
38/* Override dev tree settings per board */
39void variant_devtree_update(void)
40{
41 struct device *root = SA_DEV_ROOT;
42 config_t *cfg = root->chip_info;
43
44 /* Update PL2 based on CPU */
45 cfg->tdp_pl2_override = get_pl2();
46}