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Alexandru Gagniuc37a8a8b2013-05-21 14:51:26 -05001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20/*
21 * Inspired from the EPIA-M700
22 */
Alexandru Gagniuc37a8a8b2013-05-21 14:51:26 -050023#include <stdint.h>
24#include <device/pci_def.h>
25#include <device/pci_ids.h>
26#include <arch/io.h>
27#include <device/pnp_def.h>
28#include <arch/io.h>
29#include <arch/hlt.h>
30#include <console/console.h>
31#include <lib.h>
32#include <cpu/x86/bist.h>
33#include <string.h>
34#include <timestamp.h>
35#include <console/cbmem_console.h>
36
37#include "northbridge/via/vx900/early_vx900.h"
38#include "northbridge/via/vx900/raminit.h"
39/* FIXME: This is the only .c include we couldn't get rid of */
40#include "superio/fintek/f81865f/f81865f_early_serial.c"
41
42#define SERIAL_DEV PNP_DEV(0x4e, 0x10)
43
Alexandru Gagniuc37a8a8b2013-05-21 14:51:26 -050044/* cache_as_ram.inc jumps to here. */
45void main(unsigned long bist)
46{
47 u32 tolm;
Kyösti Mälkkic0beb6d2013-09-08 13:48:36 +030048
49 timestamp_init(rdtsc());
50 timestamp_add_now(TS_START_ROMSTAGE);
Alexandru Gagniuc37a8a8b2013-05-21 14:51:26 -050051
52 /* First thing we need to do on the VX900, before anything else */
53 vx900_enable_pci_config_space();
54
55 /* Serial console is easy to take care of */
56 f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
57 console_init();
58 print_debug("Console initialized. \n");
59
60 vx900_cpu_bus_interface_setup();
61
62 /* Be smart. Get this info */
63 vx900_print_strapping_info();
64 /* DEVEL helper */
65 vx900_disable_auto_reboot();
66 /* Halt if there was a built-in self test failure. */
67 report_bist_failure(bist);
68
69 /* Oh, almighty, give us the SMBUS */
70 enable_smbus();
71
Kyösti Mälkkic0beb6d2013-09-08 13:48:36 +030072 timestamp_add_now(TS_BEFORE_INITRAM);
Alexandru Gagniuc37a8a8b2013-05-21 14:51:26 -050073 /* Now we can worry about raminit.
74 * This board only has DDR3, so no need to worry about which DRAM type
75 * to use */
76 dimm_layout dimms = { {0x50, 0x51, SPD_END_LIST} };
77 vx900_init_dram_ddr3(&dimms);
Kyösti Mälkkic0beb6d2013-09-08 13:48:36 +030078 timestamp_add_now(TS_AFTER_INITRAM);
Alexandru Gagniuc37a8a8b2013-05-21 14:51:26 -050079
80 /* TODO: All these ram_checks are here to ensure we test most of the RAM
81 * below 4G. They should not be needed once VX900 raminit is stable */
82 ram_check(0, 0x80);
83 ram_check(512 << 10, 0x80);
84 ram_check((1 << 20) - (1 << 10), 0x80);
85 ram_check((1 << 24), 0x80);
86 ram_check((512 + 256 - 1) << 20, 0x80);
87 ram_check(0x80c0000, 0x80);
88 tolm = ((pci_read_config16(MCU, 0x84) & 0xfff0) >> 4) << 20;
89 if (tolm > (1 * (u32) GiB))
90 ram_check(1024 << 10, 0x80);
91 if (tolm > (2 * (u32) GiB))
92 ram_check(2048 << 20, 0x80);
93
94 print_debug("We passed RAM verify\n");
Kyösti Mälkkic0beb6d2013-09-08 13:48:36 +030095
Alexandru Gagniuc37a8a8b2013-05-21 14:51:26 -050096 /* We got RAM working, now we can write the timestamps to RAM */
Kyösti Mälkkif8bf5a12013-10-11 22:08:02 +030097#if CONFIG_EARLY_CBMEM_INIT
Kyösti Mälkki2d8520b2014-01-06 17:20:31 +020098 cbmem_recovery(0);
Kyösti Mälkkif8bf5a12013-10-11 22:08:02 +030099#endif
Kyösti Mälkkic0beb6d2013-09-08 13:48:36 +0300100 timestamp_add_now(TS_END_ROMSTAGE);
Alexandru Gagniuc37a8a8b2013-05-21 14:51:26 -0500101 /* FIXME: See if this is needed or take this out please */
102 /* Disable Memcard and SDIO */
103 pci_mod_config8(LPC, 0x51, 0, (1 << 7) | (1 << 4));
Alexandru Gagniuc37a8a8b2013-05-21 14:51:26 -0500104}