Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2013 Google Inc. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA |
| 18 | */ |
| 19 | |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 20 | #include <stdlib.h> |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 21 | #include <console/console.h> |
| 22 | #include <delay.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/smbus.h> |
| 25 | #include <device/pci.h> |
| 26 | #include "chip.h" |
| 27 | |
| 28 | /* Chip commands */ |
| 29 | #define RTD2132_COMMAND 0x01 |
| 30 | #define RTD2132_DATA 0x00 |
| 31 | #define RTD2132_FIRMWARE 0x80 |
| 32 | #define RTD2132_FIRMWARE_START 0x00 |
| 33 | #define RTD2132_FIRMWARE_STOP 0x01 |
| 34 | |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 35 | /* Panel Power Sequence Timing Registers. */ |
| 36 | #define RTD2132_COMMAND_PWR_SEQ_T1 0x32 /* 1ms units. */ |
| 37 | #define RTD2132_COMMAND_PWR_SEQ_T2 0x33 /* 4ms units. */ |
| 38 | #define RTD2132_COMMAND_PWR_SEQ_T3 0x34 /* 1ms units. */ |
| 39 | #define RTD2132_COMMAND_PWR_SEQ_T4 0x35 /* 1ms units. */ |
| 40 | #define RTD2132_COMMAND_PWR_SEQ_T5 0x36 /* 4ms units. */ |
| 41 | #define RTD2132_COMMAND_PWR_SEQ_T6 0x37 /* 1ms units. */ |
| 42 | #define RTD2132_COMMAND_PWR_SEQ_T7 0x38 /* 4ms units. */ |
| 43 | |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 44 | /* Spread spectrum configuration */ |
| 45 | #define RTD2132_COMMAND_SSCG_CONFIG_0 0x39 |
| 46 | #define RTD2132_SSCG_ENABLE 0xa0 |
| 47 | #define RTD2132_SSCG_DISABLE 0x20 |
| 48 | #define RTD2132_COMMAND_SSCG_CONFIG_1 0x3a |
| 49 | #define RTD2132_SSCG_CONFIG_DISABLED 0x01 /* DISABLED */ |
| 50 | #define RTD2132_SSCG_CONFIG_0_5 0x07 /* 0.5% */ |
| 51 | #define RTD2132_SSCG_CONFIG_1_0 0x0f /* 1.0% */ |
| 52 | #define RTD2132_SSCG_CONFIG_1_5 0x16 /* 1.5% */ |
| 53 | |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 54 | /* LVDS Swap */ |
| 55 | #define RTD2132_COMMAND_LVDS_SWAP 0x3b |
| 56 | #define RTD2132_LVDS_SWAP_DUAL 0x80 |
| 57 | #define RTD2132_LVDS_SWAP_NORMAL 0x04 |
| 58 | #define RTD2132_LVDS_SWAP_MIRROR 0x14 |
| 59 | #define RTD2132_LVDS_SWAP_P_N 0x24 |
| 60 | #define RTD2132_LVDS_SWAP_MIRROR_P_N 0x34 |
| 61 | #define RTD2132_LVDS_SWAP_R_L 0x0c |
| 62 | |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 63 | /* Configuration values from devicetree */ |
| 64 | #define RTD2132_SSCG_PERCENT_0_0 0x00 /* DISABLED */ |
| 65 | #define RTD2132_SSCG_PERCENT_0_5 0x05 /* 0.5% */ |
| 66 | #define RTD2132_SSCG_PERCENT_1_0 0x10 /* 1.0% */ |
| 67 | #define RTD2132_SSCG_PERCENT_1_5 0x15 /* 1.5% */ |
| 68 | |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 69 | #define RTD2132_LVDS_SWAP_CFG_DUAL 0x80 |
| 70 | #define RTD2132_LVDS_SWAP_CFG_NORMAL 0x00 |
| 71 | #define RTD2132_LVDS_SWAP_CFG_MIRROR 0x01 |
| 72 | #define RTD2132_LVDS_SWAP_CFG_P_N 0x02 |
| 73 | #define RTD2132_LVDS_SWAP_CFG_MIRROR_P_N 0x03 |
| 74 | #define RTD2132_LVDS_SWAP_CFG_R_L 0x04 |
| 75 | |
| 76 | #define RTD2132_DEBUG_REG 0 |
| 77 | |
| 78 | static void rtd2132_write_reg(device_t dev, u8 reg, u8 value) |
| 79 | { |
| 80 | if (RTD2132_DEBUG_REG) |
| 81 | printk(BIOS_DEBUG, "RTD2132 0x%02x <- 0x%02x\n", reg, value); |
| 82 | smbus_write_byte(dev, RTD2132_COMMAND, reg); |
| 83 | smbus_write_byte(dev, RTD2132_DATA, value); |
| 84 | } |
| 85 | |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 86 | static void rtd2132_firmware_stop(device_t dev) |
| 87 | { |
| 88 | smbus_write_byte(dev, RTD2132_FIRMWARE, RTD2132_FIRMWARE_STOP); |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 89 | mdelay(60); |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | static void rtd2132_firmware_start(device_t dev) |
| 93 | { |
| 94 | smbus_write_byte(dev, RTD2132_FIRMWARE, RTD2132_FIRMWARE_START); |
| 95 | } |
| 96 | |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 97 | static void rtd2132_pps(device_t dev, struct drivers_i2c_rtd2132_config *cfg) |
| 98 | { |
| 99 | /* T2, T5, and T7 register values are in units of 4ms. */ |
| 100 | rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T1, cfg->t1); |
| 101 | rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T2, cfg->t2 / 4); |
| 102 | rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T3, cfg->t3); |
| 103 | rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T4, cfg->t4); |
| 104 | rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T5, cfg->t5 / 4); |
| 105 | rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T6, cfg->t6); |
| 106 | rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T7, cfg->t7 / 4); |
| 107 | } |
| 108 | |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 109 | static void rtd2132_sscg_enable(device_t dev, u8 sscg_percent) |
| 110 | { |
| 111 | /* SSCG_Config_0 */ |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 112 | rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_0, |
| 113 | RTD2132_SSCG_ENABLE); |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 114 | |
| 115 | /* SSCG_Config_1 */ |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 116 | rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_1, sscg_percent); |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 117 | } |
| 118 | |
| 119 | static void rtd2132_sscg_disable(device_t dev) |
| 120 | { |
| 121 | /* SSCG_Config_0 */ |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 122 | rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_0, |
| 123 | RTD2132_SSCG_DISABLE); |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 124 | |
| 125 | /* SSCG_Config_1 */ |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 126 | rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_1, |
| 127 | RTD2132_SSCG_CONFIG_DISABLED); |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 128 | } |
| 129 | |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 130 | static void rtd2132_sscg(device_t dev, struct drivers_i2c_rtd2132_config *cfg) |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 131 | { |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 132 | switch (cfg->sscg_percent) { |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 133 | case RTD2132_SSCG_PERCENT_0_0: |
| 134 | printk(BIOS_INFO, "RTD2132: Disable Spread Spectrum\n"); |
| 135 | rtd2132_sscg_disable(dev); |
| 136 | break; |
| 137 | case RTD2132_SSCG_PERCENT_0_5: |
| 138 | printk(BIOS_INFO, "RTD2132: Enable 0.5%% Spread Spectrum\n"); |
| 139 | rtd2132_sscg_enable(dev, RTD2132_SSCG_CONFIG_0_5); |
| 140 | break; |
| 141 | case RTD2132_SSCG_PERCENT_1_0: |
| 142 | printk(BIOS_INFO, "RTD2132: Enable 1.0%% Spread Spectrum\n"); |
| 143 | rtd2132_sscg_enable(dev, RTD2132_SSCG_CONFIG_1_0); |
| 144 | break; |
| 145 | case RTD2132_SSCG_PERCENT_1_5: |
| 146 | printk(BIOS_INFO, "RTD2132: Enable 1.5%% Spread Spectrum\n"); |
| 147 | rtd2132_sscg_enable(dev, RTD2132_SSCG_CONFIG_1_5); |
| 148 | break; |
| 149 | default: |
| 150 | printk(BIOS_ERR, "RTD2132: Invalid Spread Spectrum 0x%02x\n", |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 151 | cfg->sscg_percent); |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 152 | } |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 153 | } |
| 154 | |
| 155 | static void rtd2132_lvds_swap(device_t dev, |
| 156 | struct drivers_i2c_rtd2132_config *cfg) |
| 157 | { |
| 158 | u8 swap_value = RTD2132_LVDS_SWAP_NORMAL; |
| 159 | |
| 160 | switch (cfg->lvds_swap & ~RTD2132_LVDS_SWAP_CFG_DUAL) { |
| 161 | case RTD2132_LVDS_SWAP_CFG_NORMAL: |
| 162 | swap_value = RTD2132_LVDS_SWAP_NORMAL; |
| 163 | break; |
| 164 | case RTD2132_LVDS_SWAP_CFG_MIRROR: |
| 165 | swap_value = RTD2132_LVDS_SWAP_MIRROR; |
| 166 | break; |
| 167 | case RTD2132_LVDS_SWAP_CFG_P_N: |
| 168 | swap_value = RTD2132_LVDS_SWAP_P_N; |
| 169 | break; |
| 170 | case RTD2132_LVDS_SWAP_CFG_MIRROR_P_N: |
| 171 | swap_value = RTD2132_LVDS_SWAP_MIRROR_P_N; |
| 172 | break; |
| 173 | case RTD2132_LVDS_SWAP_CFG_R_L: |
| 174 | swap_value = RTD2132_LVDS_SWAP_R_L; |
| 175 | break; |
| 176 | default: |
| 177 | printk(BIOS_ERR, "RTD2132: Invalid LVDS swap value 0x%02x\n", |
| 178 | cfg->lvds_swap); |
| 179 | } |
| 180 | |
| 181 | if (cfg->lvds_swap & RTD2132_LVDS_SWAP_CFG_DUAL) |
| 182 | swap_value |= RTD2132_LVDS_SWAP_DUAL; |
| 183 | |
Idwer Vollering | d26da9c | 2013-12-22 21:38:18 +0000 | [diff] [blame] | 184 | printk(BIOS_INFO, "RTD2132: LVDS Swap 0x%02x\n", swap_value); |
Aaron Durbin | ebad176 | 2013-08-14 11:27:40 -0500 | [diff] [blame] | 185 | |
| 186 | rtd2132_write_reg(dev, RTD2132_COMMAND_LVDS_SWAP, swap_value); |
| 187 | } |
| 188 | |
| 189 | static void rtd2132_defaults(device_t dev) |
| 190 | { |
| 191 | static const struct def_setting { |
| 192 | u8 reg; |
| 193 | u8 value; |
| 194 | } def_settings[] = { |
| 195 | { 0x3c, 0x06 }, |
| 196 | { 0x3d, 0x38 }, |
| 197 | { 0x3e, 0x73 }, |
| 198 | { 0x3f, 0x33 }, |
| 199 | { 0x06, 0x90 }, |
| 200 | { 0x06, 0xb0 }, |
| 201 | { 0x06, 0x80 }, |
| 202 | }; |
| 203 | int i; |
| 204 | |
| 205 | for (i = 0; i < ARRAY_SIZE(def_settings); i++) |
| 206 | rtd2132_write_reg(dev, def_settings[i].reg, |
| 207 | def_settings[i].value); |
| 208 | } |
| 209 | |
| 210 | static void rtd2132_setup(device_t dev) |
| 211 | { |
| 212 | struct drivers_i2c_rtd2132_config *config = dev->chip_info; |
| 213 | |
| 214 | if (!config) |
| 215 | return; |
| 216 | |
| 217 | /* Stop running firmware */ |
| 218 | rtd2132_firmware_stop(dev); |
| 219 | |
| 220 | /* Panel Power Sequencing Settings. */ |
| 221 | rtd2132_pps(dev, config); |
| 222 | |
| 223 | /* Spread spectrum configuration */ |
| 224 | rtd2132_sscg(dev, config); |
| 225 | |
| 226 | /* LVDS Swap Setting. */ |
| 227 | rtd2132_lvds_swap(dev, config); |
| 228 | |
| 229 | /* Default settings. */ |
| 230 | rtd2132_defaults(dev); |
Duncan Laurie | 0cf0d14 | 2013-07-15 09:11:21 -0700 | [diff] [blame] | 231 | |
| 232 | /* Start firmware */ |
| 233 | rtd2132_firmware_start(dev); |
| 234 | } |
| 235 | |
| 236 | static void rtd2132_init(device_t dev) |
| 237 | { |
| 238 | if (dev->enabled && dev->path.type == DEVICE_PATH_I2C && |
| 239 | ops_smbus_bus(get_pbus_smbus(dev))) { |
| 240 | rtd2132_setup(dev); |
| 241 | } |
| 242 | } |
| 243 | |
| 244 | static void rtd2132_noop(device_t dummy) |
| 245 | { |
| 246 | } |
| 247 | |
| 248 | static struct device_operations rtd2132_operations = { |
| 249 | .read_resources = rtd2132_noop, |
| 250 | .set_resources = rtd2132_noop, |
| 251 | .enable_resources = rtd2132_noop, |
| 252 | .init = rtd2132_init, |
| 253 | }; |
| 254 | |
| 255 | static void enable_dev(struct device *dev) |
| 256 | { |
| 257 | dev->ops = &rtd2132_operations; |
| 258 | } |
| 259 | |
| 260 | struct chip_operations drivers_i2c_rtd2132_ops = { |
| 261 | CHIP_NAME("Realtek RTD2132 LVDS Bridge") |
| 262 | .enable_dev = enable_dev, |
| 263 | }; |