Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 3 | * |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2009 coresystems GmbH |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 5 | * 2012 secunet Security Networks AG |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 20 | * MA 02110-1301 USA |
| 21 | */ |
| 22 | |
| 23 | #include <console/console.h> |
| 24 | #include <device/device.h> |
| 25 | #include <device/pci.h> |
| 26 | #include <string.h> |
| 27 | #include <cpu/cpu.h> |
| 28 | #include <cpu/x86/mtrr.h> |
| 29 | #include <cpu/x86/msr.h> |
| 30 | #include <cpu/x86/lapic.h> |
| 31 | #include <cpu/intel/microcode.h> |
Stefan Reinauer | 2a27b20 | 2010-12-11 22:14:44 +0000 | [diff] [blame] | 32 | #include <cpu/intel/speedstep.h> |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 33 | #include <cpu/intel/hyperthreading.h> |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 34 | #include <cpu/x86/cache.h> |
Uwe Hermann | aac8f66 | 2010-09-29 09:54:16 +0000 | [diff] [blame] | 35 | #include <cpu/x86/name.h> |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 36 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 37 | #include "chip.h" |
| 38 | |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 39 | static void init_timer(void) |
| 40 | { |
| 41 | /* Set the apic timer to no interrupts and periodic mode */ |
| 42 | lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); |
| 43 | |
| 44 | /* Set the divider to 1, no divider */ |
| 45 | lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); |
| 46 | |
| 47 | /* Set the initial counter to 0xffffffff */ |
| 48 | lapic_write(LAPIC_TMICT, 0xffffffff); |
| 49 | } |
| 50 | |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 51 | #define IA32_FEATURE_CONTROL 0x003a |
| 52 | |
| 53 | #define CPUID_VMX (1 << 5) |
| 54 | #define CPUID_SMX (1 << 6) |
| 55 | static void enable_vmx(void) |
| 56 | { |
| 57 | struct cpuid_result regs; |
| 58 | msr_t msr; |
| 59 | |
| 60 | msr = rdmsr(IA32_FEATURE_CONTROL); |
| 61 | |
| 62 | if (msr.lo & (1 << 0)) { |
| 63 | /* VMX locked. If we set it again we get an illegal |
| 64 | * instruction |
| 65 | */ |
| 66 | return; |
| 67 | } |
| 68 | |
| 69 | regs = cpuid(1); |
| 70 | if (regs.ecx & CPUID_VMX) { |
| 71 | msr.lo |= (1 << 2); |
| 72 | if (regs.ecx & CPUID_SMX) |
| 73 | msr.lo |= (1 << 1); |
| 74 | } |
| 75 | |
| 76 | wrmsr(IA32_FEATURE_CONTROL, msr); |
| 77 | |
| 78 | msr.lo |= (1 << 0); /* Set lock bit */ |
| 79 | |
| 80 | wrmsr(IA32_FEATURE_CONTROL, msr); |
| 81 | } |
| 82 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 83 | #define MSR_BBL_CR_CTL3 0x11e |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 84 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 85 | static void configure_c_states(const int quad) |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 86 | { |
| 87 | msr_t msr; |
| 88 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 89 | /* Find pointer to CPU configuration. */ |
| 90 | const device_t lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); |
| 91 | const struct cpu_intel_model_1067x_config *const conf = |
| 92 | (lapic && lapic->chip_info) ? lapic->chip_info : NULL; |
| 93 | |
| 94 | /* Is C5 requested and supported? */ |
| 95 | const int c5 = conf && conf->c5 && |
| 96 | (rdmsr(MSR_BBL_CR_CTL3).lo & (3 << 30)) && |
| 97 | !(rdmsr(MSR_FSB_FREQ).lo & (1 << 31)); |
| 98 | /* Is C6 requested and supported? */ |
| 99 | const int c6 = conf && conf->c6 && |
| 100 | ((cpuid_edx(5) >> (6 * 4)) & 0xf) && c5; |
| 101 | |
| 102 | const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */ |
| 103 | |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 104 | msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 105 | msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 106 | msr.lo |= (1 << 8); |
| 107 | if (quad) { |
| 108 | msr.lo = (msr.lo & ~(7 << 0)) | (4 << 0); |
| 109 | } |
| 110 | if (c5) { |
| 111 | msr.lo &= ~(1 << 13); |
| 112 | msr.lo &= ~(7 << 0); |
| 113 | msr.lo |= (1 << 3); /* Enable dynamic L2. */ |
| 114 | msr.lo |= (1 << 14); /* Enable deeper sleep */ |
| 115 | } |
| 116 | /* Next two fields seem to be mutually exclusive: */ |
| 117 | msr.lo &= ~(7 << 4); |
| 118 | msr.lo |= (1 << 10); /* Enable IO MWAIT redirection. */ |
| 119 | if (c6) |
| 120 | msr.lo |= (1 << 25); |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 121 | wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 122 | |
| 123 | /* Set Processor MWAIT IO BASE */ |
| 124 | msr.hi = 0; |
| 125 | msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 126 | wrmsr(MSR_PMG_IO_BASE_ADDR, msr); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 127 | |
| 128 | /* Set IO Capture Address */ |
| 129 | msr.hi = 0; |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 130 | msr.lo = ((PMB0_BASE + 4) & 0xffff) | ((cst_range & 0xffff) << 16); |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 131 | wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 132 | |
| 133 | if (c5) { |
| 134 | msr = rdmsr(MSR_BBL_CR_CTL3); |
| 135 | msr.lo &= ~(7 << 25); |
| 136 | msr.lo |= (2 << 25); |
| 137 | msr.lo &= ~(3 << 30); |
| 138 | msr.lo |= (1 << 30); |
| 139 | wrmsr(MSR_BBL_CR_CTL3, msr); |
| 140 | } |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 141 | } |
| 142 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 143 | static void configure_p_states(const char stepping, const char cores) |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 144 | { |
| 145 | msr_t msr; |
| 146 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 147 | /* Find pointer to CPU configuration. */ |
| 148 | const device_t lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); |
| 149 | struct cpu_intel_model_1067x_config *const conf = |
| 150 | (lapic && lapic->chip_info) ? lapic->chip_info : NULL; |
| 151 | |
| 152 | msr = rdmsr(MSR_EXTENDED_CONFIG); |
| 153 | if (conf->slfm && (msr.lo & (1 << 27))) /* Super LFM supported? */ |
| 154 | msr.lo |= (1 << 28); /* Enable Super LFM. */ |
| 155 | wrmsr(MSR_EXTENDED_CONFIG, msr); |
| 156 | |
| 157 | if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32))) { |
| 158 | /* Turbo supported? */ |
| 159 | if ((stepping == 0xa) && (cores < 4)) { |
| 160 | msr = rdmsr(MSR_FSB_FREQ); |
| 161 | msr.lo |= (1 << 3); /* Enable hysteresis. */ |
| 162 | wrmsr(MSR_FSB_FREQ, msr); |
| 163 | } |
| 164 | msr = rdmsr(IA32_PERF_CTL); |
| 165 | msr.hi &= ~(1 << (32 - 32)); /* Clear turbo disable. */ |
| 166 | wrmsr(IA32_PERF_CTL, msr); |
| 167 | } |
| 168 | |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 169 | msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 170 | msr.lo &= ~(1 << 11); /* Enable hw coordination. */ |
| 171 | msr.lo |= (1 << 15); /* Lock config until next reset. */ |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 172 | wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 173 | } |
| 174 | |
| 175 | #define MSR_EMTTM_CR_TABLE(x) (0xa8 + (x)) |
| 176 | #define MSR_EMTTM_TABLE_NUM 6 |
| 177 | static void configure_emttm_tables(void) |
| 178 | { |
| 179 | int i; |
| 180 | int num_states, pstate_idx; |
| 181 | msr_t msr; |
| 182 | sst_table_t pstates; |
| 183 | |
| 184 | /* Gather p-state information. */ |
| 185 | speedstep_gen_pstates(&pstates); |
| 186 | |
| 187 | /* Never turbo mode or Super LFM. */ |
| 188 | num_states = pstates.num_states; |
| 189 | if (pstates.states[0].is_turbo) |
| 190 | --num_states; |
| 191 | if (pstates.states[pstates.num_states - 1].is_slfm) |
| 192 | --num_states; |
| 193 | /* Repeat lowest p-state if we haven't enough states. */ |
| 194 | const int num_lowest_pstate = |
| 195 | (num_states < MSR_EMTTM_TABLE_NUM) |
| 196 | ? (MSR_EMTTM_TABLE_NUM - num_states) + 1 |
| 197 | : 1; |
| 198 | /* Start from the lowest entry but skip Super LFM. */ |
| 199 | if (pstates.states[pstates.num_states - 1].is_slfm) |
| 200 | pstate_idx = pstates.num_states - 2; |
| 201 | else |
| 202 | pstate_idx = pstates.num_states - 1; |
| 203 | for (i = 0; i < MSR_EMTTM_TABLE_NUM; ++i) { |
| 204 | if (i >= num_lowest_pstate) |
| 205 | --pstate_idx; |
| 206 | const sst_state_t *const pstate = &pstates.states[pstate_idx]; |
| 207 | printk(BIOS_DEBUG, "writing P-State %d: %d, %d, " |
| 208 | "%2d, 0x%02x, %d; encoded: 0x%04x\n", |
| 209 | pstate_idx, pstate->dynfsb, pstate->nonint, |
| 210 | pstate->ratio, pstate->vid, pstate->power, |
| 211 | SPEEDSTEP_ENCODE_STATE(*pstate)); |
| 212 | msr.hi = 0; |
| 213 | msr.lo = SPEEDSTEP_ENCODE_STATE(pstates.states[pstate_idx]) & |
| 214 | /* Don't set half ratios. */ |
| 215 | ~SPEEDSTEP_RATIO_NONINT; |
| 216 | wrmsr(MSR_EMTTM_CR_TABLE(i), msr); |
| 217 | } |
| 218 | |
| 219 | msr = rdmsr(MSR_EMTTM_CR_TABLE(5)); |
| 220 | msr.lo |= (1 << 31); /* lock tables */ |
| 221 | wrmsr(MSR_EMTTM_CR_TABLE(5), msr); |
| 222 | } |
| 223 | |
| 224 | static void configure_misc(const int eist, const int tm2, const int emttm) |
| 225 | { |
| 226 | msr_t msr; |
| 227 | |
| 228 | const u32 sub_cstates = cpuid_edx(5); |
| 229 | |
| 230 | msr = rdmsr(IA32_MISC_ENABLES); |
| 231 | msr.lo |= (1 << 3); /* TM1 enable */ |
| 232 | if (tm2) |
| 233 | msr.lo |= (1 << 13); /* TM2 enable */ |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 234 | msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */ |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 235 | msr.lo |= (1 << 18); /* MONITOR/MWAIT enable */ |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 236 | |
| 237 | msr.lo |= (1 << 10); /* FERR# multiplexing */ |
| 238 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 239 | if (eist) |
| 240 | msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 241 | |
| 242 | /* Enable C2E */ |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 243 | if (((sub_cstates >> (2 * 4)) & 0xf) >= 2) { |
| 244 | msr.lo |= (1 << 26); |
| 245 | } |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 246 | |
| 247 | /* Enable C4E */ |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 248 | if (((sub_cstates >> (4 * 4)) & 0xf) >= 2) { |
| 249 | msr.hi |= (1 << (32 - 32)); // C4E |
| 250 | msr.hi |= (1 << (33 - 32)); // Hard C4E |
| 251 | } |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 252 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 253 | /* Enable EMTTM */ |
| 254 | if (emttm) |
| 255 | msr.hi |= (1 << (36 - 32)); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 256 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 257 | /* Enable turbo mode */ |
| 258 | if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32))) |
| 259 | msr.hi &= ~(1 << (38 - 32)); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 260 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 261 | wrmsr(IA32_MISC_ENABLES, msr); |
| 262 | |
| 263 | if (eist) { |
| 264 | msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ |
| 265 | wrmsr(IA32_MISC_ENABLES, msr); |
| 266 | } |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 267 | } |
| 268 | |
| 269 | #define PIC_SENS_CFG 0x1aa |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 270 | static void configure_pic_thermal_sensors(const int tm2, const int quad) |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 271 | { |
| 272 | msr_t msr; |
| 273 | |
| 274 | msr = rdmsr(PIC_SENS_CFG); |
| 275 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 276 | if (quad) |
| 277 | msr.lo |= (1 << 31); |
| 278 | else |
| 279 | msr.lo &= ~(1 << 31); |
| 280 | if (tm2) |
| 281 | msr.lo |= (1 << 20); /* Enable TM1 if TM2 fails. */ |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 282 | msr.lo |= (1 << 21); // inter-core lock TM1 |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 283 | msr.lo |= (1 << 4); // Enable bypass filter /* What does it do? */ |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 284 | |
| 285 | wrmsr(PIC_SENS_CFG, msr); |
| 286 | } |
| 287 | |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 288 | static void model_1067x_init(device_t cpu) |
| 289 | { |
| 290 | char processor_name[49]; |
| 291 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 292 | |
| 293 | /* Gather some information: */ |
| 294 | |
| 295 | const struct cpuid_result cpuid1 = cpuid(1); |
| 296 | |
| 297 | /* Read stepping. */ |
| 298 | const char stepping = cpuid1.eax & 0xf; |
| 299 | /* Read number of cores. */ |
| 300 | const char cores = (cpuid1.ebx >> 16) & 0xf; |
| 301 | /* Is this a quad core? */ |
| 302 | const char quad = cores > 2; |
| 303 | /* Is this even a multiprocessor? */ |
| 304 | const char mp = cores > 1; |
| 305 | |
| 306 | /* Enable EMTTM on uni- and on multi-processors if it's not disabled. */ |
| 307 | const char emttm = !mp || !(rdmsr(MSR_EXTENDED_CONFIG).lo & 4); |
| 308 | |
| 309 | /* Is enhanced speedstep supported? */ |
| 310 | const char eist = (cpuid1.ecx & (1 << 7)) && |
| 311 | !(rdmsr(IA32_PLATFORM_ID).lo & (1 << 17)); |
| 312 | /* Test for TM2 only if EIST is available. */ |
| 313 | const char tm2 = eist && (cpuid1.ecx & (1 << 8)); |
| 314 | |
| 315 | |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 316 | /* Turn on caching if we haven't already */ |
| 317 | x86_enable_cache(); |
| 318 | |
| 319 | /* Update the microcode */ |
Alexandru Gagniuc | 2c38f50 | 2013-12-06 23:14:54 -0600 | [diff] [blame^] | 320 | intel_update_microcode_from_cbfs(); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 321 | |
| 322 | /* Print processor name */ |
| 323 | fill_processor_name(processor_name); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 324 | printk(BIOS_INFO, "CPU: %s.\n", processor_name); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 325 | |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 326 | /* Setup MTRRs */ |
Sven Schnelle | adfbcb79 | 2012-01-10 12:01:43 +0100 | [diff] [blame] | 327 | x86_setup_mtrrs(); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 328 | x86_mtrr_check(); |
| 329 | |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 330 | /* Enable the local cpu apics */ |
| 331 | setup_lapic(); |
| 332 | |
| 333 | /* Initialize the APIC timer */ |
| 334 | init_timer(); |
| 335 | |
| 336 | /* Enable virtualization */ |
| 337 | enable_vmx(); |
| 338 | |
| 339 | /* Configure C States */ |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 340 | configure_c_states(quad); |
| 341 | |
| 342 | /* Configure P States */ |
| 343 | configure_p_states(stepping, cores); |
| 344 | |
| 345 | /* EMTTM */ |
| 346 | if (emttm) |
| 347 | configure_emttm_tables(); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 348 | |
| 349 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 350 | configure_misc(eist, tm2, emttm); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 351 | |
| 352 | /* PIC thermal sensor control */ |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 353 | configure_pic_thermal_sensors(tm2, quad); |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 354 | |
| 355 | /* Start up my cpu siblings */ |
| 356 | intel_sibling_init(cpu); |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 357 | } |
| 358 | |
| 359 | static struct device_operations cpu_dev_ops = { |
| 360 | .init = model_1067x_init, |
| 361 | }; |
| 362 | |
| 363 | static struct cpu_device_id cpu_table[] = { |
| 364 | { X86_VENDOR_INTEL, 0x10676 }, /* Intel Core 2 Solo/Core Duo */ |
Stefan Reinauer | c104cb0 | 2010-10-18 00:21:39 +0000 | [diff] [blame] | 365 | { X86_VENDOR_INTEL, 0x10677 }, |
| 366 | { X86_VENDOR_INTEL, 0x1067A }, |
Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 367 | { 0, 0 }, |
| 368 | }; |
| 369 | |
| 370 | static const struct cpu_driver driver __cpu_driver = { |
| 371 | .ops = &cpu_dev_ops, |
| 372 | .id_table = cpu_table, |
| 373 | }; |
| 374 | |
Nico Huber | 68d7c7a | 2012-10-02 11:46:11 +0200 | [diff] [blame] | 375 | struct chip_operations cpu_intel_model_1067x_ops = { |
| 376 | CHIP_NAME("Intel Penryn CPU") |
| 377 | }; |