Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 AMD |
| 5 | * Written by Yinghai Lu <yinghailu@amd.com> for AMD. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | #define ASSEMBLY 1 |
Myles Watson | 1d6d45e | 2009-11-06 17:02:51 +0000 | [diff] [blame] | 23 | #define __PRE_RAM__ |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 24 | |
| 25 | #define RAMINIT_SYSINFO 1 |
| 26 | |
| 27 | #define K8_ALLOCATE_IO_RANGE 1 |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 28 | |
| 29 | #define QRANK_DIMM_SUPPORT 1 |
| 30 | |
| 31 | #if CONFIG_LOGICAL_CPUS==1 |
| 32 | #define SET_NB_CFG_54 1 |
| 33 | #endif |
| 34 | |
| 35 | //used by init_cpus and fidvid |
| 36 | #define K8_SET_FIDVID 0 |
| 37 | //if we want to wait for core1 done before DQS training, set it to 0 |
| 38 | #define K8_SET_FIDVID_CORE0_ONLY 1 |
| 39 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 40 | #if CONFIG_K8_REV_F_SUPPORT == 1 |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 41 | #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 |
| 42 | #endif |
| 43 | |
| 44 | #define DBGP_DEFAULT 7 |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 45 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 46 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 47 | #include <string.h> |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 48 | #include <device/pci_def.h> |
| 49 | #include <device/pci_ids.h> |
| 50 | #include <arch/io.h> |
| 51 | #include <device/pnp_def.h> |
| 52 | #include <arch/romcc_io.h> |
| 53 | #include <cpu/x86/lapic.h> |
| 54 | #include "option_table.h" |
| 55 | #include "pc80/mc146818rtc_early.c" |
| 56 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 57 | #if CONFIG_USE_FAILOVER_IMAGE==0 |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 58 | #include "pc80/serial.c" |
| 59 | #include "arch/i386/lib/console.c" |
| 60 | #if CONFIG_USBDEBUG_DIRECT |
| 61 | #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" |
| 62 | #include "pc80/usbdebug_direct_serial.c" |
| 63 | #endif |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 64 | #include "lib/ramtest.c" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 65 | |
| 66 | #include <cpu/amd/model_fxx_rev.h> |
| 67 | |
| 68 | #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" |
| 69 | #include "northbridge/amd/amdk8/raminit.h" |
| 70 | #include "cpu/amd/model_fxx/apic_timer.c" |
| 71 | #include "lib/delay.c" |
| 72 | |
| 73 | #endif |
| 74 | |
| 75 | #include "cpu/x86/lapic/boot_cpu.c" |
| 76 | #include "northbridge/amd/amdk8/reset_test.c" |
| 77 | #include "superio/winbond/w83627hf/w83627hf_early_serial.c" |
| 78 | #include "superio/winbond/w83627hf/w83627hf_early_init.c" |
| 79 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 80 | #if CONFIG_USE_FAILOVER_IMAGE==0 |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 81 | |
| 82 | #include "cpu/x86/bist.h" |
| 83 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 84 | #include "northbridge/amd/amdk8/debug.c" |
| 85 | |
| 86 | #include "cpu/amd/mtrr/amd_earlymtrr.c" |
| 87 | |
| 88 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
| 89 | |
| 90 | #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) |
| 91 | |
| 92 | #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" |
| 93 | |
| 94 | static void memreset_setup(void) |
| 95 | { |
| 96 | } |
| 97 | |
| 98 | static void memreset(int controllers, const struct mem_controller *ctrl) |
| 99 | { |
| 100 | } |
| 101 | |
| 102 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 103 | { |
| 104 | /* nothing to do */ |
| 105 | } |
| 106 | |
| 107 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 108 | { |
| 109 | return smbus_read_byte(device, address); |
| 110 | } |
| 111 | |
| 112 | #include "northbridge/amd/amdk8/amdk8_f.h" |
| 113 | #include "northbridge/amd/amdk8/coherent_ht.c" |
| 114 | |
| 115 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
| 116 | |
| 117 | #include "northbridge/amd/amdk8/raminit_f.c" |
| 118 | |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 119 | #include "lib/generic_sdram.c" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 120 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 121 | #include "resourcemap.c" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 122 | |
| 123 | #include "cpu/amd/dualcore/dualcore.c" |
| 124 | |
| 125 | #define MCP55_NUM 1 |
| 126 | #define MCP55_USE_NIC 1 |
| 127 | |
| 128 | #define MCP55_PCI_E_X_0 1 |
| 129 | |
| 130 | #define MCP55_MB_SETUP \ |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 131 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ |
| 132 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ |
| 133 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \ |
| 134 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \ |
| 135 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ |
| 136 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 137 | |
| 138 | #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" |
| 139 | #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" |
| 140 | |
| 141 | #include "cpu/amd/car/copy_and_run.c" |
| 142 | |
| 143 | #include "cpu/amd/car/post_cache_as_ram.c" |
| 144 | |
| 145 | #include "cpu/amd/model_fxx/init_cpus.c" |
| 146 | |
| 147 | #include "cpu/amd/model_fxx/fidvid.c" |
| 148 | |
| 149 | #endif |
| 150 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 151 | #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" |
| 152 | #include "northbridge/amd/amdk8/early_ht.c" |
| 153 | |
| 154 | |
| 155 | static void sio_setup(void) |
| 156 | { |
| 157 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 158 | unsigned value; |
| 159 | uint32_t dword; |
| 160 | uint8_t byte; |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 161 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 162 | byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); |
| 163 | byte |= 0x20; |
| 164 | pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); |
| 165 | |
| 166 | dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); |
| 167 | /*serial 0 */ |
| 168 | dword |= (1<<0); |
| 169 | pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); |
| 170 | |
| 171 | dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); |
| 172 | dword |= (1<<16); |
| 173 | pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 174 | |
| 175 | } |
| 176 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 177 | #if CONFIG_USE_FAILOVER_IMAGE==0 |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 178 | |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 179 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 180 | { |
| 181 | static const uint16_t spd_addr [] = { |
| 182 | (0xa<<3)|0, (0xa<<3)|2, 0, 0, |
| 183 | (0xa<<3)|1, (0xa<<3)|3, 0, 0, |
| 184 | #if CONFIG_MAX_PHYSICAL_CPUS > 1 |
| 185 | (0xa<<3)|4, (0xa<<3)|6, 0, 0, |
| 186 | (0xa<<3)|5, (0xa<<3)|7, 0, 0, |
| 187 | #endif |
| 188 | }; |
| 189 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 190 | struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 191 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 192 | int needs_reset = 0; |
| 193 | unsigned bsp_apicid = 0; |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 194 | |
Patrick Georgi | 2bd9100 | 2010-03-18 16:46:50 +0000 | [diff] [blame^] | 195 | if (!cpu_init_detectedx && boot_cpu()) { |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 196 | /* Nothing special needs to be done to find bus 0 */ |
| 197 | /* Allow the HT devices to be found */ |
| 198 | |
| 199 | enumerate_ht_chain(); |
| 200 | |
| 201 | sio_setup(); |
| 202 | |
| 203 | /* Setup the mcp55 */ |
| 204 | mcp55_enable_rom(); |
| 205 | } |
| 206 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 207 | if (bist == 0) { |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 208 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 209 | } |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 210 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 211 | w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 212 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 213 | setup_mb_resource_map(); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 214 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 215 | uart_init(); |
| 216 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 217 | /* Halt if there was a built in self test failure */ |
| 218 | report_bist_failure(bist); |
| 219 | |
| 220 | |
| 221 | #if CONFIG_USBDEBUG_DIRECT |
| 222 | mcp55_enable_usbdebug_direct(DBGP_DEFAULT); |
| 223 | early_usbdebug_direct_init(); |
| 224 | #endif |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 225 | console_init(); |
| 226 | print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n"); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 227 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 228 | print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 229 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 230 | #if CONFIG_MEM_TRAIN_SEQ == 1 |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 231 | set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 232 | #endif |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 233 | setup_coherent_ht_domain(); // routing table and start other core0 |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 234 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 235 | wait_all_core0_started(); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 236 | #if CONFIG_LOGICAL_CPUS==1 |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 237 | // It is said that we should start core1 after all core0 launched |
| 238 | /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, |
| 239 | * So here need to make sure last core0 is started, esp for two way system, |
| 240 | * (there may be apic id conflicts in that case) |
| 241 | */ |
| 242 | start_other_cores(); |
| 243 | wait_all_other_cores_started(bsp_apicid); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 244 | #endif |
| 245 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 246 | /* it will set up chains and store link pair for optimization later */ |
| 247 | ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 248 | |
| 249 | #if K8_SET_FIDVID == 1 |
| 250 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 251 | { |
| 252 | msr_t msr; |
| 253 | msr=rdmsr(0xc0010042); |
| 254 | print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 255 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 256 | } |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 257 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 258 | enable_fid_change(); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 259 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 260 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 261 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 262 | init_fidvid_bsp(bsp_apicid); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 263 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 264 | // show final fid and vid |
| 265 | { |
| 266 | msr_t msr; |
| 267 | msr=rdmsr(0xc0010042); |
| 268 | print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 269 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 270 | } |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 271 | #endif |
| 272 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 273 | needs_reset |= optimize_link_coherent_ht(); |
| 274 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 275 | needs_reset |= mcp55_early_setup_x(); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 276 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 277 | // fidvid change will issue one LDTSTOP and the HT change will be effective too |
| 278 | if (needs_reset) { |
| 279 | print_info("ht reset -\r\n"); |
| 280 | soft_reset(); |
| 281 | } |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 282 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 283 | allow_all_aps_stop(bsp_apicid); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 284 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 285 | //It's the time to set ctrl in sysinfo now; |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 286 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 287 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 288 | enable_smbus(); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 289 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 290 | memreset_setup(); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 291 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 292 | //do we need apci timer, tsc...., only debug need it for better output |
| 293 | /* all ap stopped? */ |
| 294 | // init_timer(); // Need to use TMICT to synconize FID/VID |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 295 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 296 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 297 | |
Myles Watson | a643ea3 | 2008-10-06 21:00:46 +0000 | [diff] [blame] | 298 | post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 299 | |
| 300 | } |
| 301 | |
| 302 | |
| 303 | #endif |