Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 1 | chip soc/intel/tigerlake |
| 2 | # CPU |
| 3 | # Enable Enhanced Intel SpeedStep |
| 4 | register "eist_enable" = "1" |
| 5 | |
| 6 | # Graphics |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 7 | # Not used but timings left for reference |
| 8 | # register "panel_cfg" = "{ |
Sean Rhodes | fa7970a | 2022-07-03 22:38:24 +0100 | [diff] [blame] | 9 | # .up_delay_ms = 2000, // T3 |
| 10 | # .backlight_on_delay_ms = 0, // T7 |
| 11 | # .backlight_off_delay_ms = 2000, // T9 |
| 12 | # .down_delay_ms = 500, // T10 |
| 13 | # .cycle_delay_ms = 500, // T12 |
| 14 | # .backlight_pwm_hz = 200, // PWM |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 15 | # }" |
| 16 | |
| 17 | # FSP Memory |
| 18 | register "CnviBtCore" = "true" |
| 19 | register "CnviBtAudioOffload" = "1" |
| 20 | register "enable_c6dram" = "1" |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 21 | register "SaGv" = "SaGv_Enabled" |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 22 | |
| 23 | # FSP Silicon |
| 24 | # Serial I/O |
| 25 | register "SerialIoI2cMode" = "{ |
| 26 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
Sean Rhodes | 51ab5e4 | 2021-12-20 21:35:05 +0000 | [diff] [blame] | 27 | [PchSerialIoIndexI2C4] = PchSerialIoSkipInit, |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 28 | }" |
| 29 | |
| 30 | register "SerialIoUartMode" = "{ |
| 31 | [PchSerialIoIndexUART2] = PchSerialIoSkipInit, |
| 32 | }" |
| 33 | |
| 34 | # Power |
| 35 | register "PchPmSlpS3MinAssert" = "2" # 50ms |
| 36 | register "PchPmSlpS4MinAssert" = "3" # 1s |
| 37 | register "PchPmSlpSusMinAssert" = "3" # 500ms |
| 38 | register "PchPmSlpAMinAssert" = "3" # 2s |
| 39 | |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 40 | # PM Util |
| 41 | # GPE configuration |
| 42 | # Note that GPE events called out in ASL code rely on this |
| 43 | # route. i.e. If this route changes then the affected GPE |
| 44 | # offset bits also need to be changed. |
| 45 | # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) |
| 46 | register "pmc_gpe0_dw0" = "GPP_B" |
| 47 | register "pmc_gpe0_dw1" = "GPP_C" |
| 48 | register "pmc_gpe0_dw2" = "GPP_E" |
| 49 | |
| 50 | # Enable the correct decode ranges on the LPC bus. |
| 51 | register "lpc_ioe" = "LPC_IOE_EC_4E_4F | |
| 52 | LPC_IOE_SUPERIO_2E_2F | |
| 53 | LPC_IOE_KBC_60_64 | |
| 54 | LPC_IOE_EC_62_66 | |
| 55 | LPC_IOE_LGE_200" |
| 56 | |
| 57 | # PCIe Clock |
| 58 | register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" |
| 59 | register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" |
| 60 | register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED" |
| 61 | register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED" |
| 62 | register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED" |
| 63 | register "PcieClkSrcClkReq[6]" = "PCIE_CLK_NOTUSED" |
| 64 | |
| 65 | # Actual device tree. |
Arthur Heymans | 69cd729 | 2022-11-07 13:52:11 +0100 | [diff] [blame] | 66 | device cpu_cluster 0 on end |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 67 | |
| 68 | device domain 0 on |
Sean Rhodes | 655f2e0 | 2022-08-24 22:32:12 +0100 | [diff] [blame] | 69 | device ref igpu on end |
| 70 | device ref dptf on end |
| 71 | device ref tbt_pcie_rp0 on end |
| 72 | device ref gna on end |
Sean Rhodes | e573e40 | 2023-07-19 14:07:01 +0100 | [diff] [blame] | 73 | device ref crashlog on end |
Sean Rhodes | 655f2e0 | 2022-08-24 22:32:12 +0100 | [diff] [blame] | 74 | device ref north_xhci on |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 75 | register "UsbTcPortEn" = "1" |
| 76 | register "TcssXhciEn" = "1" |
| 77 | register "TcssAuxOri" = "0" |
| 78 | end |
Sean Rhodes | 655f2e0 | 2022-08-24 22:32:12 +0100 | [diff] [blame] | 79 | device ref tbt_dma0 on |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 80 | chip drivers/intel/usb4/retimer |
| 81 | register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" |
| 82 | use tcss_usb3_port1 as dfp[0].typec_port |
| 83 | device generic 0 on end |
| 84 | end |
| 85 | end |
Sean Rhodes | 655f2e0 | 2022-08-24 22:32:12 +0100 | [diff] [blame] | 86 | device ref south_xhci on |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 87 | # Motherboard USB Type C |
| 88 | register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" |
Sean Rhodes | 2e21725 | 2022-05-26 20:52:41 +0100 | [diff] [blame] | 89 | register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" |
| 90 | |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 91 | # Motherboard USB 3.0 |
| 92 | register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" |
Sean Rhodes | 2e21725 | 2022-05-26 20:52:41 +0100 | [diff] [blame] | 93 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" |
| 94 | |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 95 | # Daughterboard USB 3.0 |
| 96 | register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" |
Sean Rhodes | 2e21725 | 2022-05-26 20:52:41 +0100 | [diff] [blame] | 97 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" |
| 98 | |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 99 | # Daughterboard SD Card |
| 100 | register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" |
Sean Rhodes | 2e21725 | 2022-05-26 20:52:41 +0100 | [diff] [blame] | 101 | |
Sean Rhodes | 2eb2dce | 2022-05-26 20:56:14 +0100 | [diff] [blame] | 102 | # Webcam |
| 103 | register "usb2_ports[CONFIG_CCD_PORT]" = "USB2_PORT_MID(OC_SKIP)" |
| 104 | |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 105 | # Internal Bluetooth |
| 106 | register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 107 | end |
Sean Rhodes | 655f2e0 | 2022-08-24 22:32:12 +0100 | [diff] [blame] | 108 | device ref shared_ram on end |
| 109 | device ref cnvi_wifi on |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 110 | chip drivers/wifi/generic |
| 111 | register "wake" = "GPE0_PME_B0" |
| 112 | device generic 0 on end |
| 113 | end |
| 114 | end |
Sean Rhodes | 655f2e0 | 2022-08-24 22:32:12 +0100 | [diff] [blame] | 115 | device ref i2c0 on |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 116 | chip drivers/i2c/hid |
| 117 | register "generic.hid" = ""STAR0001"" |
| 118 | register "generic.desc" = ""Touchpad"" |
| 119 | register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)" |
Matt DeVillier | 2cf52d8 | 2022-09-01 15:09:24 -0500 | [diff] [blame] | 120 | register "generic.detect" = "1" |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 121 | register "hid_desc_reg_offset" = "0x20" |
| 122 | device i2c 2c on end |
| 123 | end |
| 124 | end |
Sean Rhodes | 655f2e0 | 2022-08-24 22:32:12 +0100 | [diff] [blame] | 125 | device ref heci1 on end |
| 126 | device ref sata on |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 127 | register "SataSalpSupport" = "1" |
| 128 | # Port 1 |
| 129 | register "SataPortsEnable[1]" = "1" |
| 130 | register "SataPortsDevSlp[1]" = "1" |
| 131 | end |
Sean Rhodes | 655f2e0 | 2022-08-24 22:32:12 +0100 | [diff] [blame] | 132 | device ref i2c4 on end |
| 133 | device ref uart2 on end |
| 134 | device ref pcie_rp9 on |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 135 | register "HybridStorageMode" = "0" |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 136 | register "PcieRpLtrEnable[8]" = "1" |
| 137 | register "PcieClkSrcUsage[3]" = "0x08" |
| 138 | register "PcieClkSrcClkReq[3]" = "3" |
Michael Niewöhner | 45b6080 | 2022-01-08 20:47:11 +0100 | [diff] [blame] | 139 | register "PcieRpSlotImplemented[8]" = "1" |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 140 | smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" |
Stephen Edworthy | 66d94ba | 2022-03-31 09:09:32 +0100 | [diff] [blame] | 141 | chip soc/intel/common/block/pcie/rtd3 |
| 142 | register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" |
| 143 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" |
| 144 | register "srcclk_pin" = "3" |
| 145 | device generic 0 on end |
| 146 | end |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 147 | end |
Sean Rhodes | 655f2e0 | 2022-08-24 22:32:12 +0100 | [diff] [blame] | 148 | device ref gspi1 on end |
| 149 | device ref pch_espi on |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 150 | register "gen1_dec" = "0x000c1641" |
| 151 | register "gen2_dec" = "0x000c0681" |
| 152 | register "gen3_dec" = "0x000c0081" |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 153 | chip drivers/pc80/tpm |
| 154 | device pnp 0c31.0 on end |
Sean Rhodes | fa7970a | 2022-07-03 22:38:24 +0100 | [diff] [blame] | 155 | end |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 156 | |
| 157 | chip ec/starlabs/merlin |
| 158 | # Port pair 4Eh/4Fh |
| 159 | device pnp 4e.00 on end # IO Interface |
| 160 | device pnp 4e.01 off end # Com 1 |
| 161 | device pnp 4e.02 off end # Com 2 |
| 162 | device pnp 4e.04 off end # System Wake-Up |
| 163 | device pnp 4e.05 off end # PS/2 Mouse |
| 164 | device pnp 4e.06 on # PS/2 Keyboard |
| 165 | io 0x60 = 0x0060 |
| 166 | io 0x62 = 0x0064 |
| 167 | irq 0x70 = 1 |
| 168 | end |
| 169 | device pnp 4e.0a off end # Consumer IR |
| 170 | device pnp 4e.0f off end # Shared Memory/Flash Interface |
| 171 | device pnp 4e.10 off end # RTC-like Timer |
| 172 | device pnp 4e.11 off end # Power Management Channel 1 |
| 173 | device pnp 4e.12 off end # Power Management Channel 2 |
| 174 | device pnp 4e.13 off end # Serial Peripheral Interface |
| 175 | device pnp 4e.14 off end # Platform EC Interface |
| 176 | device pnp 4e.17 off end # Power Management Channel 3 |
| 177 | device pnp 4e.18 off end # Power Management Channel 4 |
| 178 | device pnp 4e.19 off end # Power Management Channel 5 |
| 179 | end |
| 180 | end |
Sean Rhodes | 25cd8e5 | 2022-08-24 22:44:28 +0100 | [diff] [blame] | 181 | device ref p2sb on end |
Sean Rhodes | dc522d2 | 2022-10-03 11:19:52 +0100 | [diff] [blame] | 182 | device ref pmc hidden |
| 183 | chip drivers/intel/pmc_mux |
| 184 | device generic 0 on |
| 185 | chip drivers/intel/pmc_mux/conn |
| 186 | use usb2_port1 as usb2_port |
| 187 | use tcss_usb3_port1 as usb3_port |
| 188 | device generic 0 alias conn0 on end |
| 189 | end |
| 190 | end |
| 191 | end |
| 192 | end |
Sean Rhodes | 655f2e0 | 2022-08-24 22:32:12 +0100 | [diff] [blame] | 193 | device ref hda on |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 194 | register "PchHdaAudioLinkHdaEnable" = "1" |
| 195 | end |
Sean Rhodes | 655f2e0 | 2022-08-24 22:32:12 +0100 | [diff] [blame] | 196 | device ref smbus on end |
Sean Rhodes | 17441a3 | 2021-07-05 16:03:15 +0100 | [diff] [blame] | 197 | end |
| 198 | end |