Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame^] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Pre-training PCIe subsystem initialization routines. |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 42 | * |
| 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | /*---------------------------------------------------------------------------------------- |
| 48 | * M O D U L E S U S E D |
| 49 | *---------------------------------------------------------------------------------------- |
| 50 | */ |
| 51 | |
| 52 | #include "AGESA.h" |
| 53 | #include "Ids.h" |
| 54 | #include "Gnb.h" |
| 55 | #include "GnbPcie.h" |
| 56 | #include "GnbPcieFamServices.h" |
| 57 | #include "PcieFamilyServices.h" |
| 58 | #include "PcieInit.h" |
| 59 | #include "PcieMiscLib.h" |
| 60 | #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) |
| 61 | #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) |
| 62 | #include GNB_MODULE_DEFINITIONS (GnbPcieTrainingV1) |
| 63 | #include "GnbRegistersON.h" |
| 64 | #include "Filecode.h" |
| 65 | #define FILECODE PROC_GNB_PCIE_PCIEINIT_FILECODE |
| 66 | /*---------------------------------------------------------------------------------------- |
| 67 | * D E F I N I T I O N S A N D M A C R O S |
| 68 | *---------------------------------------------------------------------------------------- |
| 69 | */ |
| 70 | |
| 71 | |
| 72 | /*---------------------------------------------------------------------------------------- |
| 73 | * T Y P E D E F S A N D S T R U C T U R E S |
| 74 | *---------------------------------------------------------------------------------------- |
| 75 | */ |
| 76 | |
| 77 | |
| 78 | /*---------------------------------------------------------------------------------------- |
| 79 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 80 | *---------------------------------------------------------------------------------------- |
| 81 | */ |
| 82 | |
| 83 | |
| 84 | /*----------------------------------------------------------------------------------------*/ |
| 85 | /** |
| 86 | * Control port visibility in PCI config space |
| 87 | * |
| 88 | * |
| 89 | * @param[in] Control Make port Hide/Unhide ports |
| 90 | * @param[in] Pcie Pointer to global PCIe configuration |
| 91 | */ |
| 92 | VOID |
| 93 | PciePortsVisibilityControl ( |
| 94 | IN PCIE_PORT_VISIBILITY Control, |
| 95 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 96 | ) |
| 97 | { |
| 98 | PCIe_COMPLEX_CONFIG *ComplexList; |
| 99 | ComplexList = &Pcie->ComplexList[0]; |
| 100 | while (ComplexList != NULL) { |
| 101 | PCIe_SILICON_CONFIG *SiliconList; |
| 102 | SiliconList = PcieComplexGetSiliconList (ComplexList); |
| 103 | while (SiliconList != NULL) { |
| 104 | PcieFmPortVisabilityControl (Control, SiliconList, Pcie); |
| 105 | SiliconList = PcieLibGetNextDescriptor (SiliconList); |
| 106 | } |
| 107 | ComplexList = PcieLibGetNextDescriptor (ComplexList); |
| 108 | } |
| 109 | } |
| 110 | |
| 111 | |
| 112 | PCIE_HOST_REGISTER_ENTRY CoreInitTable [] = { |
| 113 | { |
| 114 | D0F0xE4_CORE_0020_ADDRESS, |
| 115 | D0F0xE4_CORE_0020_CiRcOrderingDis_MASK | |
| 116 | D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK, |
| 117 | (0x1 << D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET) |
| 118 | }, |
| 119 | { |
| 120 | D0F0xE4_CORE_0010_ADDRESS, |
| 121 | D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_MASK, |
| 122 | (0x4 << D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_OFFSET) |
| 123 | }, |
| 124 | { |
| 125 | D0F0xE4_CORE_001C_ADDRESS, |
| 126 | D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK | |
| 127 | D0F0xE4_CORE_001C_TxArbSlvLimit_MASK | |
| 128 | D0F0xE4_CORE_001C_TxArbMstLimit_MASK, |
| 129 | (0x1 << D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET) | |
| 130 | (0x4 << D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET) | |
| 131 | (0x4 << D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET) |
| 132 | }, |
| 133 | { |
| 134 | D0F0xE4_CORE_0040_ADDRESS, |
| 135 | D0F0xE4_CORE_0040_PElecIdleMode_MASK, |
| 136 | (0x2 << D0F0xE4_CORE_0040_PElecIdleMode_OFFSET) |
| 137 | }, |
| 138 | { |
| 139 | D0F0xE4_CORE_0002_ADDRESS, |
| 140 | D0F0xE4_CORE_0002_HwDebug_0__MASK, |
| 141 | (0x1 << D0F0xE4_CORE_0002_HwDebug_0__OFFSET) |
| 142 | }, |
| 143 | { |
| 144 | D0F0xE4_CORE_00C1_ADDRESS, |
| 145 | D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK | |
| 146 | D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK, |
| 147 | (0x1 << D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET) | |
| 148 | (0x1 << D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET) |
| 149 | }, |
| 150 | { |
| 151 | D0F0xE4_CORE_00B0_ADDRESS, |
| 152 | D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK | |
| 153 | D0F0xE4_CORE_00B0_StrapF0AerEn_MASK, |
| 154 | (0x1 << D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET) |
| 155 | } |
| 156 | }; |
| 157 | |
| 158 | /*----------------------------------------------------------------------------------------*/ |
| 159 | /** |
| 160 | * Common Core Init |
| 161 | * |
| 162 | * |
| 163 | * @param[in] Wrapper Pointer to wrapper configuration descriptor |
| 164 | * @param[in] Pcie Pointer to global PCIe configuration |
| 165 | */ |
| 166 | VOID |
| 167 | PcieCommonCoreInit ( |
| 168 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 169 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 170 | ) |
| 171 | { |
| 172 | UINT8 CoreId; |
| 173 | UINTN Index; |
| 174 | if (PcieLibIsPcieWrapper (Wrapper)) { |
| 175 | IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommonCoreInit Enter\n"); |
| 176 | for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { |
| 177 | for (Index = 0; Index < sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY); Index++) { |
| 178 | UINT32 Value; |
| 179 | Value = PcieRegisterRead ( |
| 180 | Wrapper, |
| 181 | CORE_SPACE (CoreId, CoreInitTable[Index].Reg), |
| 182 | Pcie |
| 183 | ); |
| 184 | Value &= (~CoreInitTable[Index].Mask); |
| 185 | Value |= CoreInitTable[Index].Data; |
| 186 | PcieRegisterWrite ( |
| 187 | Wrapper, |
| 188 | CORE_SPACE (CoreId, CoreInitTable[Index].Reg), |
| 189 | Value, |
| 190 | FALSE, |
| 191 | Pcie |
| 192 | ); |
| 193 | } |
| 194 | } |
| 195 | IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommonCoreInit Exit\n"); |
| 196 | } |
| 197 | } |
| 198 | |
| 199 | |
| 200 | /*----------------------------------------------------------------------------------------*/ |
| 201 | /** |
| 202 | * Per wrapper Pcie Init SRBM reset prior Aaccess to wrapper registers. |
| 203 | * |
| 204 | * |
| 205 | * @param[in] Wrapper Pointer to wrapper configuration descriptor |
| 206 | * @param[in] Buffer Pointer buffer |
| 207 | * @param[in] Pcie Pointer to global PCIe configuration |
| 208 | */ |
| 209 | AGESA_STATUS |
| 210 | PcieInitSrbmCallback ( |
| 211 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 212 | IN OUT VOID *Buffer, |
| 213 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 214 | ) |
| 215 | { |
| 216 | PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie); |
| 217 | return AGESA_SUCCESS; |
| 218 | } |
| 219 | /*----------------------------------------------------------------------------------------*/ |
| 220 | /** |
| 221 | * Per wrapper Pcie Init prior training. |
| 222 | * |
| 223 | * |
| 224 | * @param[in] Wrapper Pointer to wrapper configuration descriptor |
| 225 | * @param[in] Buffer Pointer buffer |
| 226 | * @param[in] Pcie Pointer to global PCIe configuration |
| 227 | */ |
| 228 | AGESA_STATUS |
| 229 | PcieInitCallback ( |
| 230 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 231 | IN OUT VOID *Buffer, |
| 232 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 233 | ) |
| 234 | { |
| 235 | AGESA_STATUS Status; |
| 236 | PcieTopologyPrepareForReconfig (Wrapper, Pcie); |
| 237 | Status = PcieTopologySetCoreConfig (Wrapper, Pcie); |
| 238 | ASSERT (Status == AGESA_SUCCESS); |
| 239 | PcieTopologyApplyLaneMux (Wrapper, Pcie); |
| 240 | PcieFmPifSetRxDetectPowerMode (Wrapper, Pcie); |
| 241 | PciePifSetLs2ExitTime (Wrapper, Pcie); |
| 242 | PcieTopologySelectMasterPll (Wrapper, Pcie); |
| 243 | PcieTopologyExecuteReconfig (Wrapper, Pcie); |
| 244 | PcieTopologySetLinkReversal (Wrapper, Pcie); |
| 245 | PciePifApplyGanging (Wrapper, Pcie); |
| 246 | PcieFmPhyApplyGanging (Wrapper, Pcie); |
| 247 | PciePifPllInitForDdi (Wrapper, Pcie); |
| 248 | PcieTopologyLaneControl ( |
| 249 | DisableLanes, |
| 250 | PcieUtilGetWrapperLaneBitMap (LANE_TYPE_ALL, LANE_TYPE_PCIE_ALLOCATED, Wrapper, Pcie), |
| 251 | Wrapper, |
| 252 | Pcie |
| 253 | ); |
| 254 | PcieSetDdiOwnPhy (Wrapper, Pcie); |
| 255 | PciePollPifForCompeletion (Wrapper, Pcie); |
| 256 | PcieFmAvertClockPickers (Wrapper, Pcie); |
| 257 | PcieFmConfigureClock (PcieGen1, Wrapper, Pcie); |
| 258 | PcieCommonCoreInit (Wrapper, Pcie); |
| 259 | PciePifDisableFifoReset (Wrapper, Pcie); |
| 260 | return Status; |
| 261 | } |
| 262 | |
| 263 | /*----------------------------------------------------------------------------------------*/ |
| 264 | /** |
| 265 | * Pcie Init |
| 266 | * |
| 267 | * |
| 268 | * |
| 269 | * @param[in] Pcie Pointer to global PCIe configuration |
| 270 | * @retval AGESA_SUCCESS Topology successfully mapped |
| 271 | * @retval AGESA_ERROR Topology can not be mapped |
| 272 | */ |
| 273 | |
| 274 | AGESA_STATUS |
| 275 | PcieInit ( |
| 276 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 277 | ) |
| 278 | { |
| 279 | AGESA_STATUS Status; |
| 280 | AGESA_STATUS AgesaStatus; |
| 281 | IDS_HDT_CONSOLE (GNB_TRACE, "PcieInit Enter\n"); |
| 282 | AgesaStatus = AGESA_SUCCESS; |
| 283 | Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitSrbmCallback, NULL, Pcie); |
| 284 | AGESA_STATUS_UPDATE (Status, AgesaStatus); |
| 285 | PcieFmPreInit (Pcie); |
| 286 | Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitCallback, NULL, Pcie); |
| 287 | AGESA_STATUS_UPDATE (Status, AgesaStatus); |
| 288 | PcieFmSetBootUpVoltage (PcieGen1, Pcie); |
| 289 | IDS_HDT_CONSOLE (GNB_TRACE, "PcieInit Exit [%x]\n", AgesaStatus); |
| 290 | return AgesaStatus; |
| 291 | } |
| 292 | |
| 293 | |
| 294 | /*----------------------------------------------------------------------------------------*/ |
| 295 | /** |
| 296 | * Per wrapper Pcie Init prior training. |
| 297 | * |
| 298 | * |
| 299 | * @param[in] Wrapper Pointer to wrapper configuration descriptor |
| 300 | * @param[in] Buffer Pointer buffer |
| 301 | * @param[in] Pcie Pointer to global PCIe configuration |
| 302 | */ |
| 303 | AGESA_STATUS |
| 304 | PciePostInitCallback ( |
| 305 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 306 | IN OUT VOID *Buffer, |
| 307 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 308 | ) |
| 309 | { |
| 310 | AGESA_STATUS Status; |
| 311 | |
| 312 | Status = AGESA_SUCCESS; |
| 313 | PcieFmConfigureClock ( |
| 314 | PcieUtilGlobalGenCapability (PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_ALL_PORTS, Pcie), |
| 315 | Wrapper, |
| 316 | Pcie |
| 317 | ); |
| 318 | return Status; |
| 319 | } |
| 320 | |
| 321 | /*----------------------------------------------------------------------------------------*/ |
| 322 | /** |
| 323 | * Pcie Init |
| 324 | * |
| 325 | * |
| 326 | * |
| 327 | * @param[in] Pcie Pointer to global PCIe configuration |
| 328 | * @retval AGESA_SUCCESS Topology successfully mapped |
| 329 | * @retval AGESA_ERROR Topology can not be mapped |
| 330 | */ |
| 331 | |
| 332 | AGESA_STATUS |
| 333 | PciePostInit ( |
| 334 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 335 | ) |
| 336 | { |
| 337 | AGESA_STATUS Status; |
| 338 | AGESA_STATUS AgesaStatus; |
| 339 | |
| 340 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInit Enter\n"); |
| 341 | AgesaStatus = AGESA_SUCCESS; |
| 342 | Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_PCIE_WRAPPER, PciePostInitCallback, NULL, Pcie); |
| 343 | AGESA_STATUS_UPDATE (Status, AgesaStatus); |
| 344 | PcieFmSetBootUpVoltage ( |
| 345 | PcieUtilGlobalGenCapability (PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_ALL_PORTS, Pcie), |
| 346 | Pcie |
| 347 | ); |
| 348 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInit Exit [%x]\n", AgesaStatus); |
| 349 | return AgesaStatus; |
| 350 | } |
| 351 | |