| Martin Roth | a642716 | 2014-04-25 14:12:13 -0600 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2014 Sage Electronic Engineering, LLC. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | ## You should have received a copy of the GNU General Public License |
| 16 | ## along with this program; if not, write to the Free Software |
| 17 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | ## |
| 19 | |
| 20 | if PLATFORM_USES_FSP |
| 21 | |
| 22 | comment "Intel FSP" |
| 23 | |
| 24 | config HAVE_FSP_BIN |
| 25 | bool "Use Intel Firmware Support Package" |
| 26 | help |
| 27 | Select this option to add an Intel FSP binary to |
| 28 | the resulting coreboot image. |
| 29 | |
| 30 | Note: Without this binary, coreboot builds relying on the FSP |
| 31 | will not boot |
| 32 | |
| 33 | config DCACHE_RAM_BASE |
| 34 | hex |
| 35 | default 0xfef00000 |
| 36 | |
| 37 | config DCACHE_RAM_SIZE |
| 38 | hex |
| 39 | default 0x4000 |
| 40 | |
| 41 | if HAVE_FSP_BIN |
| 42 | |
| 43 | config FSP_FILE |
| 44 | string "Intel FSP binary path and filename" |
| 45 | help |
| 46 | The path and filename of the Intel FSP binary for this platform. |
| 47 | |
| 48 | config FSP_LOC |
| 49 | hex "Intel FSP Binary location in CBFS" |
| 50 | help |
| 51 | The location in CBFS that the FSP is located. This must match the |
| 52 | value that is set in the FSP binary. If the FSP needs to be moved, |
| 53 | rebase the FSP with Intel's BCT (tool). |
| 54 | |
| 55 | config ENABLE_FSP_FAST_BOOT |
| 56 | bool "Enable Fast Boot" |
| Martin Roth | 2a9b2ed | 2014-05-19 15:30:00 -0600 | [diff] [blame^] | 57 | select ENABLE_MRC_CACHE |
| Martin Roth | a642716 | 2014-04-25 14:12:13 -0600 | [diff] [blame] | 58 | default n |
| 59 | help |
| 60 | Enabling this feature will force the MRC data to be cached in NV |
| 61 | storage to be used for speeding up boot time on future reboots |
| 62 | and/or power cycles. |
| 63 | |
| 64 | config ENABLE_MRC_CACHE |
| 65 | bool |
| Martin Roth | 2a9b2ed | 2014-05-19 15:30:00 -0600 | [diff] [blame^] | 66 | default n |
| Martin Roth | a642716 | 2014-04-25 14:12:13 -0600 | [diff] [blame] | 67 | help |
| 68 | Enabling this feature will cause MRC data to be cached in NV storage. |
| 69 | This can either be used for fast boot, or just because the FSP wants |
| 70 | it to be saved. |
| 71 | |
| 72 | config MRC_CACHE_SIZE |
| 73 | hex "Fast Boot Data Cache Size" |
| 74 | default 0x10000 |
| 75 | depends on ENABLE_MRC_CACHE |
| 76 | help |
| 77 | This is the amount of space in NV storage that is reserved for the |
| 78 | fast boot data cache storage. |
| 79 | |
| 80 | WARNING: Because this area will be erased and re-written, the size |
| 81 | should be a full sector of the flash ROM chip and nothing else should |
| 82 | be included in CBFS in any sector that the fast boot cache data is in. |
| 83 | |
| 84 | config OVERRIDE_CACHE_CACHE_LOC |
| 85 | bool |
| 86 | help |
| 87 | Selected by the platform to set a new default location for the |
| 88 | MRC/fast boot cache. |
| 89 | |
| 90 | config MRC_CACHE_LOC_OVERRIDE |
| 91 | hex |
| 92 | help |
| 93 | Sets the override CBFS location of the MRC/fast boot cache. |
| 94 | |
| 95 | config MRC_CACHE_LOC |
| 96 | hex "Fast Boot Data Cache location in CBFS" |
| 97 | default MRC_CACHE_LOC_OVERRIDE if OVERRIDE_CACHE_CACHE_LOC |
| 98 | default 0xfff50000 |
| 99 | depends on ENABLE_MRC_CACHE |
| 100 | help |
| 101 | The location in CBFS for the MRC data to be cached. |
| 102 | |
| 103 | WARNING: This should be on a sector boundary of the BIOS ROM chip |
| 104 | and nothing else should be included in that sector, or IT WILL BE |
| 105 | ERASED. |
| 106 | |
| 107 | config VIRTUAL_ROM_SIZE |
| 108 | hex "Virtual ROM Size" |
| 109 | default ROM_SIZE |
| 110 | depends on ENABLE_MRC_CACHE |
| 111 | help |
| 112 | This is used to calculate the offset of the MRC data cache in NV |
| 113 | Storage for fast boot. If in doubt, leave this set to the default |
| 114 | which sets the virtual size equal to the ROM size. |
| 115 | |
| 116 | Example: Cougar Canyon 2 has two 8 MB SPI ROMs. When the SPI ROMs are |
| 117 | loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB. When |
| 118 | the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM |
| 119 | size is 16 MB. |
| 120 | |
| 121 | endif #HAVE_FSP_BIN |
| 122 | |
| 123 | config CACHE_ROM_SIZE_OVERRIDE |
| 124 | hex "Cache ROM Size" |
| 125 | default CBFS_SIZE |
| 126 | help |
| 127 | This is the size of the cachable area that is passed into the FSP in |
| 128 | the early initialization. Typically this should be the size of the CBFS |
| 129 | area, but the size must be a power of 2 whereas the CBFS size does not |
| 130 | have this limitation. |
| 131 | |
| 132 | config USE_GENERIC_FSP_CAR_INC |
| 133 | bool |
| 134 | default n |
| 135 | help |
| 136 | The chipset can select this to use a generic cache_as_ram.inc file |
| 137 | that should be good for all FSP based platforms. |
| 138 | |
| 139 | config FSP_USES_UPD |
| 140 | bool |
| 141 | default n |
| 142 | help |
| 143 | If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig. |
| 144 | endif #PLATFORM_USES_FSP |