Jan Samek | a2035cc | 2022-11-21 09:59:53 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <baseboard/variants.h> |
| 4 | #include <bootstate.h> |
Jan Samek | 2a959be | 2023-01-17 15:39:24 +0100 | [diff] [blame^] | 5 | #include <device/mmio.h> |
Jan Samek | a2035cc | 2022-11-21 09:59:53 +0100 | [diff] [blame] | 6 | #include <gpio.h> |
Jan Samek | a2035cc | 2022-11-21 09:59:53 +0100 | [diff] [blame] | 7 | #include <soc/pci_devs.h> |
Jan Samek | a2035cc | 2022-11-21 09:59:53 +0100 | [diff] [blame] | 8 | |
| 9 | #define HOSTCTRL2 0x3E |
| 10 | #define HOSTCTRL2_PRESET (1 << 15) |
| 11 | #define SD_CAP_BYP 0x810 |
| 12 | #define SD_CAP_BYP_EN 0x5A |
| 13 | #define SD_CAP_BYP_REG1 0x814 |
| 14 | #define SD_CAP_BYP_SDR50 (1 << 13) |
| 15 | #define SD_CAP_BYP_SDR104 (1 << 14) |
| 16 | #define SD_CAP_BYP_DDR50 (1 << 15) |
| 17 | |
| 18 | void variant_mainboard_final(void) |
| 19 | { |
| 20 | struct device *dev; |
| 21 | |
Jan Samek | a2035cc | 2022-11-21 09:59:53 +0100 | [diff] [blame] | 22 | /* Limit SD-Card speed to DDR50 mode to avoid SDR104/SDR50 modes due to |
| 23 | layout limitations. */ |
| 24 | dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); |
| 25 | if (dev) { |
| 26 | uint32_t reg; |
| 27 | uint16_t reg16; |
| 28 | struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); |
| 29 | if (!res) |
| 30 | return; |
| 31 | write32(res2mmio(res, SD_CAP_BYP, 0), SD_CAP_BYP_EN); |
| 32 | reg = read32(res2mmio(res, SD_CAP_BYP_REG1, 0)); |
| 33 | /* Disable SDR104 and SDR50 mode while keeping DDR50 mode enabled. */ |
| 34 | reg &= ~(SD_CAP_BYP_SDR104 | SD_CAP_BYP_SDR50); |
| 35 | reg |= SD_CAP_BYP_DDR50; |
| 36 | write32(res2mmio(res, SD_CAP_BYP_REG1, 0), reg); |
| 37 | |
| 38 | /* Use preset driver strength from preset value registers. */ |
| 39 | reg16 = read16(res2mmio(res, HOSTCTRL2, 0)); |
| 40 | reg16 |= HOSTCTRL2_PRESET; |
| 41 | write16(res2mmio(res, HOSTCTRL2, 0), reg16); |
| 42 | } |
| 43 | } |
| 44 | |
| 45 | static void finalize_boot(void *unused) |
| 46 | { |
| 47 | /* Set coreboot ready LED. */ |
| 48 | gpio_output(GPP_F20, 1); |
| 49 | } |
| 50 | |
| 51 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); |