Ronald G. Minnich | 2a66d6b | 2013-03-28 17:01:43 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 2013 Google Inc. |
| 3 | * Copyright © 2008 Keith Packard |
| 4 | * |
| 5 | * Permission to use, copy, modify, distribute, and sell this software and its |
| 6 | * documentation for any purpose is hereby granted without fee, provided that |
| 7 | * the above copyright notice appear in all copies and that both that copyright |
| 8 | * notice and this permission notice appear in supporting documentation, and |
| 9 | * that the name of the copyright holders not be used in advertising or |
| 10 | * publicity pertaining to distribution of the software without specific, |
| 11 | * written prior permission. The copyright holders make no representations |
| 12 | * about the suitability of this software for any purpose. It is provided "as |
| 13 | * is" without express or implied warranty. |
| 14 | * |
| 15 | * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, |
| 16 | * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO |
| 17 | * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR |
| 18 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, |
| 19 | * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 20 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE |
| 21 | * OF THIS SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | #ifndef _DRM_DP_HELPER_H_ |
| 25 | #define _DRM_DP_HELPER_H_ |
| 26 | |
| 27 | /* From the VESA DisplayPort spec */ |
| 28 | |
| 29 | #define AUX_NATIVE_WRITE 0x8 |
| 30 | #define AUX_NATIVE_READ 0x9 |
| 31 | #define AUX_I2C_WRITE 0x0 |
| 32 | #define AUX_I2C_READ 0x1 |
| 33 | #define AUX_I2C_STATUS 0x2 |
| 34 | #define AUX_I2C_MOT 0x4 |
| 35 | |
| 36 | #define AUX_NATIVE_REPLY_ACK (0x0 << 4) |
| 37 | #define AUX_NATIVE_REPLY_NACK (0x1 << 4) |
| 38 | #define AUX_NATIVE_REPLY_DEFER (0x2 << 4) |
| 39 | #define AUX_NATIVE_REPLY_MASK (0x3 << 4) |
| 40 | |
| 41 | #define AUX_I2C_REPLY_ACK (0x0 << 6) |
| 42 | #define AUX_I2C_REPLY_NACK (0x1 << 6) |
| 43 | #define AUX_I2C_REPLY_DEFER (0x2 << 6) |
| 44 | #define AUX_I2C_REPLY_MASK (0x3 << 6) |
| 45 | |
| 46 | /* AUX CH addresses */ |
| 47 | /* DPCD */ |
| 48 | #define DP_DPCD_REV 0x000 |
| 49 | |
| 50 | #define DP_MAX_LINK_RATE 0x001 |
| 51 | |
| 52 | #define DP_MAX_LANE_COUNT 0x002 |
| 53 | # define DP_MAX_LANE_COUNT_MASK 0x1f |
| 54 | # define DP_TPS3_SUPPORTED (1 << 6) |
| 55 | # define DP_ENHANCED_FRAME_CAP (1 << 7) |
| 56 | |
| 57 | #define DP_MAX_DOWNSPREAD 0x003 |
| 58 | # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) |
| 59 | |
| 60 | #define DP_NORP 0x004 |
| 61 | |
| 62 | #define DP_DOWNSTREAMPORT_PRESENT 0x005 |
| 63 | # define DP_DWN_STRM_PORT_PRESENT (1 << 0) |
| 64 | # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 |
| 65 | /* 00b = DisplayPort */ |
| 66 | /* 01b = Analog */ |
| 67 | /* 10b = TMDS or HDMI */ |
| 68 | /* 11b = Other */ |
| 69 | # define DP_FORMAT_CONVERSION (1 << 3) |
| 70 | |
| 71 | #define DP_MAIN_LINK_CHANNEL_CODING 0x006 |
| 72 | |
| 73 | #define DP_EDP_CONFIGURATION_CAP 0x00d |
| 74 | #define DP_TRAINING_AUX_RD_INTERVAL 0x00e |
| 75 | |
| 76 | #define DP_PSR_SUPPORT 0x070 |
| 77 | # define DP_PSR_IS_SUPPORTED 1 |
| 78 | #define DP_PSR_CAPS 0x071 |
| 79 | # define DP_PSR_NO_TRAIN_ON_EXIT 1 |
| 80 | # define DP_PSR_SETUP_TIME_330 (0 << 1) |
| 81 | # define DP_PSR_SETUP_TIME_275 (1 << 1) |
| 82 | # define DP_PSR_SETUP_TIME_220 (2 << 1) |
| 83 | # define DP_PSR_SETUP_TIME_165 (3 << 1) |
| 84 | # define DP_PSR_SETUP_TIME_110 (4 << 1) |
| 85 | # define DP_PSR_SETUP_TIME_55 (5 << 1) |
| 86 | # define DP_PSR_SETUP_TIME_0 (6 << 1) |
| 87 | # define DP_PSR_SETUP_TIME_MASK (7 << 1) |
| 88 | # define DP_PSR_SETUP_TIME_SHIFT 1 |
| 89 | |
| 90 | /* link configuration */ |
| 91 | #define DP_LINK_BW_SET 0x100 |
| 92 | # define DP_LINK_BW_1_62 0x06 |
| 93 | # define DP_LINK_BW_2_7 0x0a |
| 94 | # define DP_LINK_BW_5_4 0x14 |
| 95 | |
| 96 | #define DP_LANE_COUNT_SET 0x101 |
| 97 | # define DP_LANE_COUNT_MASK 0x0f |
| 98 | # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) |
| 99 | |
| 100 | #define DP_TRAINING_PATTERN_SET 0x102 |
| 101 | # define DP_TRAINING_PATTERN_DISABLE 0 |
| 102 | # define DP_TRAINING_PATTERN_1 1 |
| 103 | # define DP_TRAINING_PATTERN_2 2 |
| 104 | # define DP_TRAINING_PATTERN_3 3 |
| 105 | # define DP_TRAINING_PATTERN_MASK 0x3 |
| 106 | |
| 107 | # define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) |
| 108 | # define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) |
| 109 | # define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) |
| 110 | # define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) |
| 111 | # define DP_LINK_QUAL_PATTERN_MASK (3 << 2) |
| 112 | |
| 113 | # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) |
| 114 | # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) |
| 115 | |
| 116 | # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) |
| 117 | # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) |
| 118 | # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) |
| 119 | # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) |
| 120 | |
| 121 | #define DP_TRAINING_LANE0_SET 0x103 |
| 122 | #define DP_TRAINING_LANE1_SET 0x104 |
| 123 | #define DP_TRAINING_LANE2_SET 0x105 |
| 124 | #define DP_TRAINING_LANE3_SET 0x106 |
| 125 | |
| 126 | # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 |
| 127 | # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 |
| 128 | # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) |
| 129 | # define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) |
| 130 | # define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) |
| 131 | # define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) |
| 132 | # define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) |
| 133 | |
| 134 | # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) |
| 135 | # define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) |
| 136 | # define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) |
| 137 | # define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) |
| 138 | # define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) |
| 139 | |
| 140 | # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 |
| 141 | # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) |
| 142 | |
| 143 | #define DP_DOWNSPREAD_CTRL 0x107 |
| 144 | # define DP_SPREAD_AMP_0_5 (1 << 4) |
| 145 | |
| 146 | #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 |
| 147 | # define DP_SET_ANSI_8B10B (1 << 0) |
| 148 | |
| 149 | #define DP_PSR_EN_CFG 0x170 |
| 150 | # define DP_PSR_ENABLE (1 << 0) |
| 151 | # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) |
| 152 | # define DP_PSR_CRC_VERIFICATION (1 << 2) |
| 153 | # define DP_PSR_FRAME_CAPTURE (1 << 3) |
| 154 | |
| 155 | #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 |
| 156 | # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) |
| 157 | # define DP_AUTOMATED_TEST_REQUEST (1 << 1) |
| 158 | # define DP_CP_IRQ (1 << 2) |
| 159 | # define DP_SINK_SPECIFIC_IRQ (1 << 6) |
| 160 | |
| 161 | #define DP_EDP_CONFIGURATION_SET 0x10a |
| 162 | |
| 163 | #define DP_LANE0_1_STATUS 0x202 |
| 164 | #define DP_LANE2_3_STATUS 0x203 |
| 165 | # define DP_LANE_CR_DONE (1 << 0) |
| 166 | # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) |
| 167 | # define DP_LANE_SYMBOL_LOCKED (1 << 2) |
| 168 | |
| 169 | #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ |
| 170 | DP_LANE_CHANNEL_EQ_DONE | \ |
| 171 | DP_LANE_SYMBOL_LOCKED) |
| 172 | |
| 173 | #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 |
| 174 | |
| 175 | #define DP_INTERLANE_ALIGN_DONE (1 << 0) |
| 176 | #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) |
| 177 | #define DP_LINK_STATUS_UPDATED (1 << 7) |
| 178 | |
| 179 | #define DP_SINK_STATUS 0x205 |
| 180 | |
| 181 | #define DP_RECEIVE_PORT_0_STATUS (1 << 0) |
| 182 | #define DP_RECEIVE_PORT_1_STATUS (1 << 1) |
| 183 | |
| 184 | #define DP_ADJUST_REQUEST_LANE0_1 0x206 |
| 185 | #define DP_ADJUST_REQUEST_LANE2_3 0x207 |
| 186 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 |
| 187 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 |
| 188 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c |
| 189 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 |
| 190 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 |
| 191 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 |
| 192 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 |
| 193 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 |
| 194 | |
| 195 | #define DP_TEST_REQUEST 0x218 |
| 196 | # define DP_TEST_LINK_TRAINING (1 << 0) |
| 197 | # define DP_TEST_LINK_PATTERN (1 << 1) |
| 198 | # define DP_TEST_LINK_EDID_READ (1 << 2) |
| 199 | # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ |
| 200 | |
| 201 | #define DP_TEST_LINK_RATE 0x219 |
| 202 | # define DP_LINK_RATE_162 (0x6) |
| 203 | # define DP_LINK_RATE_27 (0xa) |
| 204 | |
| 205 | #define DP_TEST_LANE_COUNT 0x220 |
| 206 | |
| 207 | #define DP_TEST_PATTERN 0x221 |
| 208 | |
| 209 | #define DP_TEST_RESPONSE 0x260 |
| 210 | # define DP_TEST_ACK (1 << 0) |
| 211 | # define DP_TEST_NAK (1 << 1) |
| 212 | # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) |
| 213 | |
| 214 | #define DP_SET_POWER 0x600 |
| 215 | # define DP_SET_POWER_D0 0x1 |
| 216 | # define DP_SET_POWER_D3 0x2 |
| 217 | |
| 218 | #define DP_PSR_ERROR_STATUS 0x2006 |
| 219 | # define DP_PSR_LINK_CRC_ERROR (1 << 0) |
| 220 | # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) |
| 221 | |
| 222 | #define DP_PSR_ESI 0x2007 |
| 223 | # define DP_PSR_CAPS_CHANGE (1 << 0) |
| 224 | |
| 225 | #define DP_PSR_STATUS 0x2008 |
| 226 | # define DP_PSR_SINK_INACTIVE 0 |
| 227 | # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 |
| 228 | # define DP_PSR_SINK_ACTIVE_RFB 2 |
| 229 | # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 |
| 230 | # define DP_PSR_SINK_ACTIVE_RESYNC 4 |
| 231 | # define DP_PSR_SINK_INTERNAL_ERROR 7 |
| 232 | # define DP_PSR_SINK_STATE_MASK 0x07 |
| 233 | |
| 234 | #define MODE_I2C_START 1 |
| 235 | #define MODE_I2C_WRITE 2 |
| 236 | #define MODE_I2C_READ 4 |
| 237 | #define MODE_I2C_STOP 8 |
| 238 | |
| 239 | #endif /* _DRM_DP_HELPER_H_ */ |