Kerry Sheh | 6b909f2 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Kerry Sheh | 6b909f2 | 2012-02-07 20:31:40 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <stdint.h> |
| 17 | #include "NbPlatform.h" |
| 18 | #include "rd890_cfg.h" |
| 19 | #include "nb_cimx.h" |
| 20 | |
| 21 | |
| 22 | /** |
| 23 | * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b |
| 24 | * |
| 25 | * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, |
| 26 | * Disable all Pcie Bridges to work around It. |
| 27 | */ |
| 28 | void sr56x0_rd890_disable_pcie_bridge(void) |
| 29 | { |
| 30 | u32 nb_dev; |
| 31 | u32 mask; |
| 32 | u32 val; |
| 33 | AMD_NB_CONFIG_BLOCK cfg_block; |
| 34 | AMD_NB_CONFIG_BLOCK *cfg_ptr = &cfg_block; |
| 35 | AMD_NB_CONFIG *nb_cfg = &(cfg_block.Northbridges[0]); |
| 36 | |
| 37 | nb_cfg->ConfigPtr = &cfg_ptr; |
| 38 | nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); |
| 39 | val = (1 << 2) | (1 << 3); /*GPP1*/ |
| 40 | val |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/ |
| 41 | val |= (1 << 18) | (1 << 19); /*GPP2*/ |
| 42 | val |= (1 << 20); /*GPP3b*/ |
| 43 | mask = ~val; |
| 44 | LibNbPciIndexRMW(nb_dev | NB_MISC_INDEX, NB_MISC_REG0C, |
| 45 | AccessS3SaveWidth32, |
| 46 | mask, |
| 47 | val, |
| 48 | nb_cfg); |
| 49 | } |
| 50 | |
| 51 | |
| 52 | /** |
| 53 | * @brief South Bridge CIMx romstage entry, |
| 54 | * wrapper of AmdPowerOnResetInit entry point. |
| 55 | */ |
| 56 | void nb_Poweron_Init(void) |
| 57 | { |
| 58 | NB_CONFIG nb_cfg[MAX_NB_COUNT]; |
| 59 | HT_CONFIG ht_cfg[MAX_NB_COUNT]; |
| 60 | PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; |
| 61 | AMD_NB_CONFIG_BLOCK gConfig; |
| 62 | AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig; |
| 63 | AGESA_STATUS status; |
| 64 | |
| 65 | printk(BIOS_DEBUG, "cimx/rd890 early.c %s() Start\n", __func__); |
| 66 | CIMX_INIT_TRACE(); |
| 67 | CIMX_TRACE((BIOS_DEBUG, "NbPowerOnResetInit entry\n")); |
| 68 | rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); |
| 69 | |
| 70 | if (ConfigPtr->StandardHeader.CalloutPtr != NULL) { |
| 71 | ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetNbPorConfig, 0, &gConfig); |
| 72 | } |
| 73 | |
| 74 | status = AmdPowerOnResetInit(&gConfig); |
| 75 | printk(BIOS_DEBUG, "cimx/rd890 early.c %s() End. return status=%x\n", __func__, status); |
| 76 | } |
| 77 | |
| 78 | /** |
| 79 | * @brief South Bridge CIMx romstage entry, |
| 80 | * wrapper of AmdHtInit entry point. |
| 81 | */ |
| 82 | void nb_Ht_Init(void) |
| 83 | { |
| 84 | AGESA_STATUS status; |
| 85 | NB_CONFIG nb_cfg[MAX_NB_COUNT]; |
| 86 | HT_CONFIG ht_cfg[MAX_NB_COUNT]; |
| 87 | PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; |
| 88 | AMD_NB_CONFIG_BLOCK gConfig; |
| 89 | AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig; |
| 90 | u32 i; |
| 91 | |
| 92 | rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); |
| 93 | |
| 94 | //Initialize HT structure |
| 95 | LibSystemApiCall(AmdHtInitializer, &gConfig); |
| 96 | for (i = 0; i < MAX_NB_COUNT; i ++) { |
| 97 | if (ConfigPtr->StandardHeader.CalloutPtr != NULL) { |
| 98 | ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetHtConfig, 0, (VOID*)&(gConfig.Northbridges[i])); |
| 99 | } |
| 100 | } |
| 101 | |
| 102 | status = LibSystemApiCall(AmdHtInit, &gConfig); |
| 103 | printk(BIOS_DEBUG, "AmdHtInit status: %x\n", status); |
| 104 | } |
| 105 | |
| 106 | void nb_S3_Init(void) |
| 107 | { |
| 108 | //TODO |
| 109 | } |