Tim Crawford | 29f1b79 | 2024-05-21 14:54:51 -0600 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <mainboard/gpio.h> |
| 4 | #include <soc/gpio.h> |
| 5 | |
| 6 | static const struct pad_config gpio_table[] = { |
| 7 | /* ------- GPIO Group GPD ------- */ |
| 8 | PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // BATLOW# |
| 9 | PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT |
| 10 | PAD_NC(GPD2, NONE), |
| 11 | PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN# |
| 12 | PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH |
| 13 | PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH |
| 14 | PAD_NC(GPD6, NONE), |
| 15 | PAD_NC(GPD7, NONE), |
| 16 | PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // CNVI_SUSCLK |
| 17 | PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN# |
| 18 | PAD_NC(GPD10, NONE), |
| 19 | PAD_NC(GPD11, NONE), |
| 20 | PAD_NC(GPD12, NONE), |
| 21 | |
| 22 | /* ------- GPIO Group GPP_A ------- */ |
| 23 | PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC |
| 24 | PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC |
| 25 | PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC |
| 26 | PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC |
| 27 | PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC# |
| 28 | PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK_EC |
| 29 | PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET# |
| 30 | PAD_NC(GPP_A7, NONE), |
| 31 | PAD_NC(GPP_A8, NONE), |
| 32 | PAD_NC(GPP_A9, NONE), |
| 33 | PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1), // ESPI_ALRT0# |
| 34 | PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), // GPIO4_GC6_NVVDD_EN_R |
| 35 | PAD_NC(GPP_A12, NONE), |
| 36 | PAD_NC(GPP_A13, NONE), |
| 37 | PAD_NC(GPP_A14, NONE), |
| 38 | |
| 39 | /* ------- GPIO Group GPP_B ------- */ |
| 40 | _PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x3000), // TPM_PIRQ# |
| 41 | PAD_NC(GPP_B1, NONE), |
| 42 | PAD_CFG_GPI(GPP_B2, NONE, DEEP), // CNVI_WAKE# |
| 43 | PAD_CFG_GPO(GPP_B3, 1, PLTRST), // BT_EN |
| 44 | PAD_NC(GPP_B4, NONE), |
| 45 | PAD_NC(GPP_B5, NONE), |
| 46 | PAD_NC(GPP_B6, NONE), |
| 47 | PAD_NC(GPP_B7, NONE), |
| 48 | PAD_NC(GPP_B8, NONE), |
| 49 | PAD_NC(GPP_B9, NONE), |
| 50 | PAD_NC(GPP_B10, NONE), |
| 51 | PAD_NC(GPP_B11, NONE), |
| 52 | PAD_NC(GPP_B12, NONE), |
| 53 | PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# |
| 54 | PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // HDA_SPKR |
| 55 | PAD_NC(GPP_B15, NONE), |
| 56 | PAD_NC(GPP_B16, NONE), |
| 57 | PAD_NC(GPP_B17, NONE), |
| 58 | PAD_CFG_NF(GPP_B18, NONE, PWROK, NF1), // GPP_B18_PMCALERT# |
| 59 | PAD_NC(GPP_B19, NONE), |
| 60 | PAD_CFG_GPO(GPP_B20, 0, DEEP), // GPIO_LANRTD3 |
| 61 | PAD_NC(GPP_B21, NONE), |
| 62 | PAD_NC(GPP_B22, NONE), |
| 63 | PAD_CFG_GPI(GPP_B23, NONE, DEEP), // Crystal freq strap |
| 64 | |
| 65 | /* ------- GPIO Group GPP_C ------- */ |
| 66 | PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK |
| 67 | PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA |
| 68 | PAD_CFG_GPI(GPP_C2, NONE, DEEP), // TLS confidentiality strap |
| 69 | PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3), // I2C2_SDA (Pantone) |
| 70 | PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3), // I2C2_SCL (Pantone) |
| 71 | PAD_NC(GPP_C5, NONE), // eSPI disable strap |
| 72 | PAD_CFG_NF(GPP_C6, NONE, DEEP, NF2), // SMD_7411 |
| 73 | PAD_CFG_NF(GPP_C7, NONE, DEEP, NF2), // SMC_7411 |
| 74 | PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET |
| 75 | PAD_NC(GPP_C9, NONE), |
| 76 | PAD_CFG_GPO(GPP_C10, 0, DEEP), // TEST_R (ANX7411) |
| 77 | PAD_CFG_GPO(GPP_C11, 0, DEEP), // PCH_TEST_R_2 (ANX7411) |
| 78 | PAD_NC(GPP_C12, NONE), |
| 79 | PAD_NC(GPP_C13, NONE), |
| 80 | PAD_NC(GPP_C14, NONE), |
| 81 | PAD_NC(GPP_C15, NONE), |
| 82 | PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP |
| 83 | PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP |
| 84 | PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // SMD_7411_2 |
| 85 | PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // SMC_7411_2 |
| 86 | // GPP_C20 (UART2_RXD) configured in bootblock |
| 87 | // GPP_C21 (UART2_TXD) configured in bootblock |
| 88 | PAD_NC(GPP_C22, NONE), |
| 89 | PAD_NC(GPP_C23, NONE), |
| 90 | |
| 91 | /* ------- GPIO Group GPP_D ------- */ |
| 92 | PAD_NC(GPP_D0, NONE), |
| 93 | PAD_NC(GPP_D1, NONE), |
| 94 | PAD_NC(GPP_D2, NONE), |
| 95 | PAD_CFG_GPO(GPP_D3, 0, DEEP), // GFX_DETECT_STRAP |
| 96 | PAD_NC(GPP_D4, NONE), |
| 97 | PAD_CFG_GPO(GPP_D5, 1, DEEP), // M.2_BT_PCMFRM_CRF_RST_N |
| 98 | // GPP_D6 (M.2_BT_PCMOUT_CLKREQ0) configured by FSP |
| 99 | PAD_NC(GPP_D7, NONE), |
| 100 | PAD_NC(GPP_D8, NONE), |
| 101 | PAD_NC(GPP_D9, NONE), |
| 102 | PAD_NC(GPP_D10, NONE), |
| 103 | PAD_NC(GPP_D11, NONE), |
| 104 | // GPP_D12 (SSD2_CLKREQ#) configured by FSP |
| 105 | PAD_NC(GPP_D13, NONE), |
| 106 | PAD_NC(GPP_D14, NONE), |
| 107 | PAD_NC(GPP_D15, NONE), |
| 108 | PAD_NC(GPP_D16, NONE), |
| 109 | PAD_NC(GPP_D17, NONE), |
| 110 | PAD_NC(GPP_D18, NONE), |
| 111 | PAD_NC(GPP_D19, NONE), |
| 112 | PAD_NC(GPP_D20, NONE), |
| 113 | PAD_NC(GPP_D21, NONE), |
| 114 | PAD_NC(GPP_D22, NONE), |
| 115 | PAD_NC(GPP_D23, NONE), |
| 116 | |
| 117 | /* ------- GPIO Group GPP_E ------- */ |
| 118 | PAD_NC(GPP_E0, NONE), |
| 119 | PAD_NC(GPP_E1, NONE), |
| 120 | PAD_CFG_GPI(GPP_E2, NONE, DEEP), // SWI# |
| 121 | PAD_NC(GPP_E3, NONE), |
| 122 | PAD_NC(GPP_E4, NONE), |
| 123 | PAD_NC(GPP_E5, NONE), |
| 124 | PAD_NC(GPP_E6, NONE), |
| 125 | PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, LEVEL), // TP_ATTN# |
| 126 | PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED# |
| 127 | PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0# |
| 128 | PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1# |
| 129 | PAD_CFG_GPI(GPP_E11, NONE, DEEP), // USB_OC2# |
| 130 | PAD_CFG_GPI(GPP_E12, NONE, DEEP), // USB_OC3# |
| 131 | PAD_NC(GPP_E13, NONE), |
| 132 | PAD_NC(GPP_E14, NONE), |
| 133 | PAD_NC(GPP_E15, NONE), |
| 134 | PAD_NC(GPP_E16, NONE), |
| 135 | PAD_CFG_GPI(GPP_E17, NONE, DEEP), // SB_KBCRST# |
| 136 | PAD_CFG_GPO(GPP_E18, 1, DEEP), // SB_BLON |
| 137 | PAD_NC(GPP_E19, NONE), |
| 138 | PAD_NC(GPP_E20, NONE), |
| 139 | PAD_NC(GPP_E21, NONE), |
| 140 | |
| 141 | /* ------- GPIO Group GPP_F ------- */ |
| 142 | PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // M.2_SSD_SATA_DET_N |
| 143 | PAD_NC(GPP_F1, NONE), |
| 144 | PAD_NC(GPP_F2, NONE), |
| 145 | PAD_NC(GPP_F3, NONE), |
| 146 | PAD_NC(GPP_F4, NONE), |
| 147 | PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), // SSD_SATA_DEVSLP |
| 148 | PAD_NC(GPP_F6, NONE), |
| 149 | _PAD_CFG_STRUCT(GPP_F7, 0x80100100, 0x0000), // 7411_INTP_OUT |
| 150 | PAD_NC(GPP_F8, NONE), |
| 151 | // GPP_F9 (DGPU_PWR_EN) configured in bootblock |
| 152 | PAD_CFG_GPI(GPP_F10, NONE, DEEP), // Recovery strap |
| 153 | PAD_NC(GPP_F11, NONE), |
| 154 | PAD_NC(GPP_F12, NONE), |
| 155 | PAD_NC(GPP_F13, NONE), |
| 156 | PAD_NC(GPP_F14, NONE), |
| 157 | PAD_CFG_GPI(GPP_F15, NONE, DEEP), // H_SKTOCC_N |
| 158 | _PAD_CFG_STRUCT(GPP_F16, 0x80100100, 0x0000), // INTP_OUT |
| 159 | PAD_NC(GPP_F17, NONE), |
| 160 | PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_WP# |
| 161 | PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD |
| 162 | PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON |
| 163 | PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS |
| 164 | PAD_NC(GPP_F22, NONE), |
| 165 | PAD_NC(GPP_F23, NONE), |
| 166 | |
| 167 | /* ------- GPIO Group GPP_G ------- */ |
| 168 | PAD_CFG_GPO(GPP_G0, 0, DEEP), // Board ID 2 |
| 169 | PAD_CFG_GPO(GPP_G1, 0, DEEP), // Board ID 3 |
| 170 | PAD_NC(GPP_G2, NONE), |
| 171 | PAD_CFG_GPI(GPP_G3, NONE, DEEP), // MB detect GN20/GN21 |
| 172 | PAD_CFG_GPI(GPP_G4, NONE, DEEP), // Board ID 1 |
| 173 | PAD_NC(GPP_G5, NONE), |
| 174 | PAD_CFG_GPI(GPP_G6, NONE, DEEP), // MB detect G-SYNC |
| 175 | PAD_CFG_GPI(GPP_G7, NONE, DEEP), // MB detect 230W/180W adapter |
| 176 | |
| 177 | /* ------- GPIO Group GPP_H ------- */ |
| 178 | PAD_CFG_GPI(GPP_H0, NONE, DEEP), // VAL_SV_ADVANCE_STRAP |
| 179 | PAD_CFG_GPO(GPP_H1, 0, DEEP), // Pantone detect |
| 180 | PAD_CFG_GPI(GPP_H2, NONE, DEEP), // WLAN_GPIO_WAKE_N |
| 181 | // GPP_H3 (NC) configured by FSP |
| 182 | // GPP_H4 (SSD1_SATA_CLKREQ#) configured by FSP |
| 183 | // GPP_H5 (WLAN_CLKREQ#) configured by FSP |
| 184 | // GPP_H6 (NC) configured by FSP |
| 185 | // GPP_H7 (LAN_CLKREQ#) configured by FSP |
| 186 | // GPP_H8 (PEG_CLKREQ#) configured by FSP |
| 187 | // GPP_H9 (SSD3_CLKREQ#) configured by FSP |
| 188 | PAD_NC(GPP_H10, NONE), |
| 189 | PAD_NC(GPP_H11, NONE), |
| 190 | PAD_NC(GPP_H12, NONE), |
| 191 | PAD_NC(GPP_H13, NONE), |
| 192 | PAD_NC(GPP_H14, NONE), |
| 193 | PAD_CFG_GPO(GPP_H15, 0, DEEP), // JTAG ODT strap |
| 194 | PAD_NC(GPP_H16, NONE), |
| 195 | PAD_NC(GPP_H17, NONE), |
| 196 | PAD_CFG_GPO(GPP_H18, 0, DEEP), // 1.8V VCCPSPI strap |
| 197 | PAD_NC(GPP_H19, NONE), |
| 198 | PAD_NC(GPP_H20, NONE), |
| 199 | PAD_NC(GPP_H21, NONE), |
| 200 | PAD_NC(GPP_H22, NONE), |
| 201 | PAD_NC(GPP_H23, NONE), |
| 202 | |
| 203 | /* ------- GPIO Group GPP_I ------- */ |
| 204 | PAD_NC(GPP_I0, NONE), |
| 205 | PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // DP_HPD |
| 206 | PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), // HDMI_HPD |
| 207 | PAD_NC(GPP_I3, NONE), |
| 208 | PAD_NC(GPP_I4, NONE), |
| 209 | PAD_NC(GPP_I5, NONE), |
| 210 | PAD_NC(GPP_I6, NONE), |
| 211 | PAD_NC(GPP_I7, NONE), |
| 212 | PAD_NC(GPP_I8, NONE), |
| 213 | PAD_NC(GPP_I9, NONE), |
| 214 | PAD_NC(GPP_I10, NONE), |
| 215 | PAD_CFG_GPI(GPP_I11, NONE, DEEP), // USB_OC4# |
| 216 | PAD_CFG_GPI(GPP_I12, NONE, DEEP), // USB_OC5# |
| 217 | PAD_CFG_GPI(GPP_I13, NONE, DEEP), // USB_OC6# |
| 218 | PAD_CFG_GPI(GPP_I14, NONE, DEEP), // USB_OC7# |
| 219 | PAD_NC(GPP_I15, NONE), |
| 220 | PAD_NC(GPP_I16, NONE), |
| 221 | PAD_NC(GPP_I17, NONE), |
| 222 | PAD_CFG_GPO(GPP_I18, 0, DEEP), // No reboot strap |
| 223 | PAD_NC(GPP_I19, NONE), |
| 224 | PAD_NC(GPP_I20, NONE), |
| 225 | PAD_NC(GPP_I21, NONE), |
| 226 | PAD_CFG_GPO(GPP_I22, 0, DEEP), // Boot BIOS strap |
| 227 | |
| 228 | /* ------- GPIO Group GPP_J ------- */ |
| 229 | PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING |
| 230 | PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // CPU_C10_GATE# |
| 231 | PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), // CNVI_BRI_DT_R / Xtal freq strap |
| 232 | PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1), // CNVI_BRI_RSP |
| 233 | PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_RGI_DT_R / M.2 CNV modes strap |
| 234 | PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_RSP |
| 235 | PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD |
| 236 | PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD |
| 237 | PAD_CFG_GPI(GPP_J8, NONE, DEEP), // VAL_TEST_SETUP_MENU |
| 238 | PAD_NC(GPP_J9, NONE), |
| 239 | PAD_NC(GPP_J10, NONE), |
| 240 | PAD_NC(GPP_J11, NONE), |
| 241 | |
| 242 | /* ------- GPIO Group GPP_K ------- */ |
| 243 | PAD_NC(GPP_K0, NONE), |
| 244 | PAD_NC(GPP_K1, NONE), |
| 245 | PAD_NC(GPP_K2, NONE), |
| 246 | PAD_NC(GPP_K3, NONE), |
| 247 | PAD_NC(GPP_K4, NONE), |
| 248 | PAD_NC(GPP_K5, NONE), |
| 249 | // GPP_K6 not in schematics |
| 250 | // GPP_K7 not in schematics |
| 251 | PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // VCCIN_AUX_VID0 |
| 252 | PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // VCCIN_AUX_VID1 |
| 253 | // GPP_K10 not in schematics |
| 254 | PAD_NC(GPP_K11, NONE), |
| 255 | |
| 256 | /* ------- GPIO Group GPP_R ------- */ |
| 257 | PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK |
| 258 | PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC |
| 259 | PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE |
| 260 | PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 |
| 261 | PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#_R |
| 262 | PAD_NC(GPP_R5, NONE), |
| 263 | PAD_NC(GPP_R6, NONE), |
| 264 | PAD_NC(GPP_R7, NONE), |
| 265 | PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD |
| 266 | PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1), // EDP_HPD |
| 267 | PAD_NC(GPP_R10, NONE), |
| 268 | PAD_NC(GPP_R11, NONE), |
| 269 | PAD_NC(GPP_R12, NONE), |
| 270 | PAD_NC(GPP_R13, NONE), |
| 271 | PAD_NC(GPP_R14, NONE), |
| 272 | PAD_NC(GPP_R15, NONE), |
| 273 | // GPP_R16 (DGPU_RST#_PCH) configured in bootblock |
| 274 | PAD_NC(GPP_R17, NONE), |
| 275 | PAD_NC(GPP_R18, NONE), |
| 276 | PAD_CFG_GPI(GPP_R19, NONE, DEEP), // SCI# |
| 277 | PAD_NC(GPP_R20, NONE), |
| 278 | PAD_NC(GPP_R21, NONE), |
| 279 | |
| 280 | /* ------- GPIO Group GPP_S ------- */ |
| 281 | PAD_NC(GPP_S0, NONE), |
| 282 | PAD_NC(GPP_S1, NONE), |
| 283 | PAD_NC(GPP_S2, NONE), |
| 284 | PAD_NC(GPP_S3, NONE), |
| 285 | PAD_NC(GPP_S4, NONE), |
| 286 | PAD_NC(GPP_S5, NONE), |
| 287 | PAD_NC(GPP_S6, NONE), |
| 288 | PAD_NC(GPP_S7, NONE), |
| 289 | }; |
| 290 | |
| 291 | void mainboard_configure_gpios(void) |
| 292 | { |
| 293 | gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); |
| 294 | } |