| Nicolas Reinecke | 29d358e | 2015-01-31 19:20:50 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * Copyright (C) 2014 Vladimir Serbinenko |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | #include <arch/byteorder.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <device/pci_def.h> |
| 25 | #include <console/console.h> |
| 26 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 27 | #include <southbridge/intel/bd82x6x/pch.h> |
| 28 | |
| 29 | void pch_enable_lpc(void) |
| 30 | { |
| 31 | /* EC Decode Range Port60/64, Port62/66 */ |
| 32 | /* Enable EC, PS/2 Keyboard/Mouse */ |
| 33 | pci_write_config16(PCH_LPC_DEV, LPC_EN, |
| 34 | CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | |
| 35 | COMA_LPC_EN); |
| 36 | |
| 37 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); |
| 38 | pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); |
| 39 | pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); |
| 40 | |
| 41 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); |
| 42 | |
| 43 | pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000); |
| 44 | } |
| 45 | |
| 46 | void rcba_config(void) |
| 47 | { |
| 48 | /* Disable unused devices (board specific) */ |
| 49 | RCBA32(FD) = 0x17e81fe3; |
| 50 | RCBA32(BUC) = 0; |
| 51 | } |
| 52 | |
| 53 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 54 | { 1, 0, 0 }, /* P0: , OC 0 */ |
| 55 | { 1, 1, 1 }, /* P1: (EHCI debug), OC 1 */ |
| 56 | { 1, 1, 3 }, /* P2: OC 3 */ |
| 57 | { 1, 0, -1 }, /* P3: no OC */ |
| 58 | { 1, 2, -1 }, /* P4: no OC */ |
| 59 | { 1, 1, -1 }, /* P5: no OC */ |
| 60 | { 1, 1, -1 }, /* P6: no OC */ |
| 61 | { 0, 1, -1 }, /* P7: empty, no OC */ |
| 62 | { 1, 1, -1 }, /* P8: smart card reader, no OC */ |
| 63 | { 1, 0, 5 }, /* P9: (EHCI debug), OC 5 */ |
| 64 | { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ |
| 65 | { 1, 1, -1 }, /* P11: bluetooth, no OC. */ |
| 66 | { 0, 0, -1 }, /* P12: wlan, no OC */ |
| 67 | { 1, 1, -1 }, /* P13: camera, no OC */ |
| 68 | }; |
| 69 | |
| 70 | void mainboard_get_spd(spd_raw_data *spd) { |
| 71 | read_spd(&spd[0], 0x50); |
| 72 | read_spd(&spd[2], 0x51); |
| 73 | } |