blob: a521d86bb0cf7d4cc4272122c2a3d8d40072a5c5 [file] [log] [blame]
Uwe Hermann9da69f82007-11-30 02:08:26 +00001/*
Stefan Reinauer7e61e452008-01-18 10:35:56 +00002 * This file is part of the coreboot project.
Uwe Hermann9da69f82007-11-30 02:08:26 +00003 *
4 * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <stdint.h>
22#include <console/console.h>
23#include <device/device.h>
24#include <device/pci.h>
25#include <device/pci_ids.h>
26#include <pc80/isa-dma.h>
27#include <pc80/mc146818rtc.h>
28#include "i82371eb.h"
29
30static void isa_init(struct device *dev)
31{
32 u16 reg16;
33 u32 reg32;
34
35 /* Initialize the real time clock (RTC). */
36 rtc_init(0);
37
38 /* Enable access to all BIOS regions. */
39 reg16 = pci_read_config16(dev, XBCS);
40 reg16 |= LOWER_BIOS_ENABLE;
41 reg16 |= EXT_BIOS_ENABLE;
42 reg16 |= EXT_BIOS_ENABLE_1MB;
43 reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */
44 pci_write_config16(dev, XBCS, reg16);
45
46 /*
47 * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO)
48 * bus, which is a subset of ISA. We select the full ISA bus here.
49 */
50 reg32 = pci_read_config32(dev, GENCFG);
51 reg32 |= ISA; /* Select ISA, not EIO. */
52 pci_write_config16(dev, GENCFG, reg32);
53
54 /* Initialize ISA DMA. */
55 isa_dma_init();
56}
57
Myles Watson29cc9ed2009-07-02 18:56:24 +000058static void sb_read_resources(struct device *dev)
59{
60 struct resource *res;
61
62 pci_dev_read_resources(dev);
63
64 res = new_resource(dev, 1);
65 res->base = 0x0UL;
66 res->size = 0x1000UL;
67 res->limit = 0xffffUL;
68 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
69
70 res = new_resource(dev, 2);
71 res->base = 0xff800000UL;
72 res->size = 0x00800000UL; /* 8 MB for flash */
73 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
74
75 res = new_resource(dev, 3); /* IOAPIC */
76 res->base = 0xfec00000;
77 res->size = 0x00001000;
78 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
79}
80
81const struct device_operations isa_ops = {
82 .read_resources = sb_read_resources,
Uwe Hermann9da69f82007-11-30 02:08:26 +000083 .set_resources = pci_dev_set_resources,
84 .enable_resources = pci_dev_enable_resources,
85 .init = isa_init,
86 .scan_bus = scan_static_bus, /* TODO: Needed? */
87 .enable = 0,
88 .ops_pci = 0, /* No subsystem IDs on 82371EB! */
89};
90
91static const struct pci_driver isa_driver __pci_driver = {
92 .ops = &isa_ops,
93 .vendor = PCI_VENDOR_ID_INTEL,
94 .device = PCI_DEVICE_ID_INTEL_82371AB_ISA,
95};
Myles Watson0520d552009-05-11 22:44:14 +000096
97static const struct pci_driver isa_SB_driver __pci_driver = {
98 .ops = &isa_ops,
99 .vendor = PCI_VENDOR_ID_INTEL,
100 .device = PCI_DEVICE_ID_INTEL_82371SB_ISA,
101};