Angel Pons | f94ac9a | 2020-04-05 15:46:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 2 | |
Kyösti Mälkki | de64078 | 2019-12-03 07:30:26 +0200 | [diff] [blame] | 3 | #include <arch/bootblock.h> |
Angel Pons | 9debbd6 | 2021-01-28 12:42:53 +0100 | [diff] [blame] | 4 | #include <assert.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 6 | #include <soc/pci_devs.h> |
| 7 | #include <soc/systemagent.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 8 | |
Angel Pons | 9debbd6 | 2021-01-28 12:42:53 +0100 | [diff] [blame] | 9 | static uint32_t encode_pciexbar_length(void) |
| 10 | { |
| 11 | switch (CONFIG_MMCONF_BUS_NUMBER) { |
| 12 | case 256: return 0 << 1; |
| 13 | case 128: return 1 << 1; |
| 14 | case 64: return 2 << 1; |
| 15 | default: return dead_code_t(uint32_t); |
| 16 | } |
| 17 | } |
| 18 | |
Arthur Heymans | 5bb15f1 | 2018-12-22 16:02:25 +0100 | [diff] [blame] | 19 | void bootblock_early_northbridge_init(void) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 20 | { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 21 | /* |
Angel Pons | 9debbd6 | 2021-01-28 12:42:53 +0100 | [diff] [blame] | 22 | * The "io" variant of the config access is explicitly used to setup the |
| 23 | * PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all |
| 24 | * subsequent non-explicit config accesses use MCFG. This code also assumes |
| 25 | * that bootblock_northbridge_init() is the first thing called in the non-asm |
| 26 | * boot block code. The final assumption is that no assembly code is using the |
Martin Roth | f48acbd | 2020-07-24 12:24:27 -0600 | [diff] [blame] | 27 | * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 28 | * |
Angel Pons | 9debbd6 | 2021-01-28 12:42:53 +0100 | [diff] [blame] | 29 | * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 30 | */ |
Angel Pons | 9debbd6 | 2021-01-28 12:42:53 +0100 | [diff] [blame] | 31 | const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; |
| 32 | pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, 0); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 33 | pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg); |
| 34 | } |