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review.coreboot.org / coreboot / 29647d97c5e66484ab5c8b56ede57329ab5410c4 / . / src / mainboard / broadcom / blast / Kconfig
blob: 474d39011a9eb4cdef02c4ca49f05a097fbe7bea [file] [log] [blame]
Patrick Georgi91ff0df2009-10-09 12:32:52 +0000[diff] [blame]1config BOARD_BROADCOM_BLAST
2 bool "Blast"
3 select ARCH_X86
Patrick Georgi91ff0df2009-10-09 12:32:52 +0000[diff] [blame]4 select CPU_AMD_SOCKET_940
5 select NORTHBRIDGE_AMD_AMDK8
6 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
7 select SOUTHBRIDGE_BROADCOM_BCM5780
8 select SOUTHBRIDGE_BROADCOM_BCM5785
9 select SUPERIO_NSC_PC87417
10 select HAVE_PIRQ_TABLE
Myles Watsonb8e20272009-10-15 13:35:47 +0000[diff] [blame]11 select HAVE_MP_TABLE
Patrick Georgi91ff0df2009-10-09 12:32:52 +0000[diff] [blame]12 select USE_PRINTK_IN_CAR
13 select USE_DCACHE_RAM
14 select HAVE_HARD_RESET
Uwe Hermannd65509d2009-10-16 17:37:20 +0000[diff] [blame]15 select BOARD_ROMSIZE_KB_512
Patrick Georgi29647d92010-01-25 07:56:01 +0000[diff] [blame^]16 select SB_HT_CHAIN_UNITID_OFFSET_ONLY
Patrick Georgi91ff0df2009-10-09 12:32:52 +0000[diff] [blame]17
18config MAINBOARD_DIR
19 string
20 default broadcom/blast
21 depends on BOARD_BROADCOM_BLAST
22
23config DCACHE_RAM_BASE
24 hex
25 default 0xcf000
26 depends on BOARD_BROADCOM_BLAST
27
28config DCACHE_RAM_SIZE
29 hex
30 default 0x01000
31 depends on BOARD_BROADCOM_BLAST
32
33config DCACHE_RAM_GLOBAL_VAR_SIZE
34 hex
35 default 0x0
36 depends on BOARD_BROADCOM_BLAST
37
38config APIC_ID_OFFSET
39 hex
40 default 0x10
41 depends on BOARD_BROADCOM_BLAST
42
43config SB_HT_CHAIN_ON_BUS0
44 int
Patrick Georgi29647d92010-01-25 07:56:01 +0000[diff] [blame^]45 default 1
Patrick Georgi91ff0df2009-10-09 12:32:52 +0000[diff] [blame]46 depends on BOARD_BROADCOM_BLAST
47
48config LB_CKS_RANGE_END
49 int
50 default 122
51 depends on BOARD_BROADCOM_BLAST
52
53config LB_CKS_LOC
54 int
55 default 123
56 depends on BOARD_BROADCOM_BLAST
57
58config MAINBOARD_PART_NUMBER
59 string
Uwe Hermann4e015eb2009-10-20 13:55:35 +0000[diff] [blame]60 default "Blast"
Patrick Georgi91ff0df2009-10-09 12:32:52 +0000[diff] [blame]61 depends on BOARD_BROADCOM_BLAST
62
63config HW_MEM_HOLE_SIZEK
64 hex
65 default 0x100000
66 depends on BOARD_BROADCOM_BLAST
67
68config MAX_CPUS
69 int
70 default 4
71 depends on BOARD_BROADCOM_BLAST
72
73config MAX_PHYSICAL_CPUS
74 int
75 default 2
76 depends on BOARD_BROADCOM_BLAST
77
78config HT_CHAIN_END_UNITID_BASE
79 hex
Patrick Georgi29647d92010-01-25 07:56:01 +0000[diff] [blame^]80 default 0x1
Patrick Georgi91ff0df2009-10-09 12:32:52 +0000[diff] [blame]81 depends on BOARD_BROADCOM_BLAST
82
83config HT_CHAIN_UNITID_BASE
84 hex
Patrick Georgi29647d92010-01-25 07:56:01 +0000[diff] [blame^]85 default 0x6
Patrick Georgi91ff0df2009-10-09 12:32:52 +0000[diff] [blame]86 depends on BOARD_BROADCOM_BLAST
87
88config USE_INIT
89 bool
90 default n
91 depends on BOARD_BROADCOM_BLAST
92
93config SB_HT_CHAIN_ON_BUS0
94 int
95 default 2
96 depends on BOARD_BROADCOM_BLAST
97
98config IRQ_SLOT_COUNT
99 int
100 default 11
101 depends on BOARD_BROADCOM_BLAST
Patrick Georgi4638c922009-11-27 11:03:20 +0000[diff] [blame]102
103config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
104 hex
105 default 0x161f
106 depends on BOARD_BROADCOM_BLAST
107
108config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
109 hex
110 default 0x3050
111 depends on BOARD_BROADCOM_BLAST
112