blob: d4db98e67ef1bb8e36199764564b5cec6340c174 [file] [log] [blame]
Gaggery Tsai7130ca02018-07-31 15:55:54 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2018 Google Inc.
5 * Copyright (C) 2018 Intel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <baseboard/variants.h>
18#include <chip.h>
19#include <device/device.h>
20#include <device/pci_ids.h>
21#include <device/pci_ops.h>
22
23#define PL2_AML 18
24#define PL2_KBL 15
25
26static uint32_t get_pl2(void)
27{
28 uint16_t id;
29 id = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID);
30 /* Assume we only have KLB-Y and AML-Y SKUs */
31 if (id == PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM)
32 return PL2_KBL;
33
34 return PL2_AML;
35}
36
37/* Override dev tree settings per board */
38void variant_devtree_update(void)
39{
Kyösti Mälkki28dc7dc2019-07-12 13:10:19 +030040 config_t *cfg = config_of_path(SA_DEVFN_ROOT);
Gaggery Tsai7130ca02018-07-31 15:55:54 -070041
42 /* Update PL2 based on CPU */
43 cfg->tdp_pl2_override = get_pl2();
44}