Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame^] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | chip soc/amd/picasso |
| 4 | register "acp_pin_cfg" = "I2S_PINS_MAX_HDA" |
| 5 | |
| 6 | # Set FADT Configuration |
| 7 | register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" |
| 8 | register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec |
| 9 | |
| 10 | register "emmc_config" = "{ |
| 11 | .timing = SD_EMMC_DISABLE, |
| 12 | }" |
| 13 | |
| 14 | register "has_usb2_phy_tune_params" = "1" |
| 15 | |
| 16 | # Controller0 Port0 Default |
| 17 | register "usb_2_port_tune_params[0]" = "{ |
| 18 | .com_pds_tune = 0x03, |
| 19 | .sq_rx_tune = 0x3, |
| 20 | .tx_fsls_tune = 0x3, |
| 21 | .tx_pre_emp_amp_tune = 0x03, |
| 22 | .tx_pre_emp_pulse_tune = 0x0, |
| 23 | .tx_rise_tune = 0x1, |
| 24 | .tx_vref_tune = 0x6, |
| 25 | .tx_hsxv_tune = 0x3, |
| 26 | .tx_res_tune = 0x01, |
| 27 | }" |
| 28 | |
| 29 | # Controller0 Port1 Default |
| 30 | register "usb_2_port_tune_params[1]" = "{ |
| 31 | .com_pds_tune = 0x03, |
| 32 | .sq_rx_tune = 0x3, |
| 33 | .tx_fsls_tune = 0x3, |
| 34 | .tx_pre_emp_amp_tune = 0x03, |
| 35 | .tx_pre_emp_pulse_tune = 0x0, |
| 36 | .tx_rise_tune = 0x1, |
| 37 | .tx_vref_tune = 0x6, |
| 38 | .tx_hsxv_tune = 0x3, |
| 39 | .tx_res_tune = 0x01, |
| 40 | }" |
| 41 | |
| 42 | # Controller0 Port2 Default |
| 43 | register "usb_2_port_tune_params[2]" = "{ |
| 44 | .com_pds_tune = 0x03, |
| 45 | .sq_rx_tune = 0x3, |
| 46 | .tx_fsls_tune = 0x3, |
| 47 | .tx_pre_emp_amp_tune = 0x03, |
| 48 | .tx_pre_emp_pulse_tune = 0x0, |
| 49 | .tx_rise_tune = 0x1, |
| 50 | .tx_vref_tune = 0x6, |
| 51 | .tx_hsxv_tune = 0x3, |
| 52 | .tx_res_tune = 0x01, |
| 53 | }" |
| 54 | |
| 55 | # Controller0 Port3 Default |
| 56 | register "usb_2_port_tune_params[3]" = "{ |
| 57 | .com_pds_tune = 0x03, |
| 58 | .sq_rx_tune = 0x3, |
| 59 | .tx_fsls_tune = 0x3, |
| 60 | .tx_pre_emp_amp_tune = 0x03, |
| 61 | .tx_pre_emp_pulse_tune = 0x0, |
| 62 | .tx_rise_tune = 0x1, |
| 63 | .tx_vref_tune = 0x6, |
| 64 | .tx_hsxv_tune = 0x3, |
| 65 | .tx_res_tune = 0x01, |
| 66 | }" |
| 67 | |
| 68 | # Controller0 Port4 Default |
| 69 | register "usb_2_port_tune_params[4]" = "{ |
| 70 | .com_pds_tune = 0x03, |
| 71 | .sq_rx_tune = 0x3, |
| 72 | .tx_fsls_tune = 0x3, |
| 73 | .tx_pre_emp_amp_tune = 0x02, |
| 74 | .tx_pre_emp_pulse_tune = 0x0, |
| 75 | .tx_rise_tune = 0x1, |
| 76 | .tx_vref_tune = 0x5, |
| 77 | .tx_hsxv_tune = 0x3, |
| 78 | .tx_res_tune = 0x01, |
| 79 | }" |
| 80 | |
| 81 | # Controller0 Port5 Default |
| 82 | register "usb_2_port_tune_params[5]" = "{ |
| 83 | .com_pds_tune = 0x03, |
| 84 | .sq_rx_tune = 0x3, |
| 85 | .tx_fsls_tune = 0x3, |
| 86 | .tx_pre_emp_amp_tune = 0x02, |
| 87 | .tx_pre_emp_pulse_tune = 0x0, |
| 88 | .tx_rise_tune = 0x1, |
| 89 | .tx_vref_tune = 0x5, |
| 90 | .tx_hsxv_tune = 0x3, |
| 91 | .tx_res_tune = 0x01, |
| 92 | }" |
| 93 | |
| 94 | # USB OC pin mapping; all ports share one OC pin |
| 95 | register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" |
| 96 | register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" |
| 97 | register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_0" |
| 98 | register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_0" |
| 99 | register "usb_port_overcurrent_pin[4]" = "USB_OC_PIN_0" |
| 100 | register "usb_port_overcurrent_pin[5]" = "USB_OC_PIN_0" |
| 101 | |
| 102 | # SPI Configuration |
| 103 | register "common_config.spi_config" = "{ |
| 104 | .normal_speed = SPI_SPEED_33M, /* MHz */ |
| 105 | .fast_speed = SPI_SPEED_66M, /* MHz */ |
| 106 | .altio_speed = SPI_SPEED_33M, /* MHz */ |
| 107 | .tpm_speed = SPI_SPEED_33M, /* MHz */ |
| 108 | .read_mode = SPI_READ_MODE_QUAD114, |
| 109 | }" |
| 110 | |
| 111 | # eSPI Configuration |
| 112 | register "common_config.espi_config" = "{ |
| 113 | .std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN, |
| 114 | .generic_io_range[0] = { |
| 115 | .base = 0x662, |
| 116 | .size = 8, |
| 117 | }, |
| 118 | |
| 119 | .io_mode = ESPI_IO_MODE_SINGLE, |
| 120 | .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, |
| 121 | .crc_check_enable = 1, |
| 122 | .dedicated_alert_pin = 1, |
| 123 | .periph_ch_en = 0, |
| 124 | .vw_ch_en = 0, |
| 125 | .oob_ch_en = 0, |
| 126 | .flash_ch_en = 0, |
| 127 | }" |
| 128 | |
| 129 | # genral purpose PCIe clock output configuration |
| 130 | register "gpp_clk_config[0]" = "GPP_CLK_REQ" |
| 131 | register "gpp_clk_config[1]" = "GPP_CLK_REQ" |
| 132 | register "gpp_clk_config[2]" = "GPP_CLK_REQ" |
| 133 | register "gpp_clk_config[3]" = "GPP_CLK_OFF" |
| 134 | register "gpp_clk_config[4]" = "GPP_CLK_REQ" |
| 135 | register "gpp_clk_config[5]" = "GPP_CLK_OFF" |
| 136 | register "gpp_clk_config[6]" = "GPP_CLK_OFF" |
| 137 | |
| 138 | device cpu_cluster 0 on |
| 139 | device lapic 0 on end |
| 140 | end |
| 141 | device domain 0 on |
| 142 | subsystemid 0x1022 0x1510 inherit |
| 143 | device pci 0.0 on end # Root Complex |
| 144 | device pci 0.2 on end # IOMMU |
| 145 | device pci 1.0 on end # Dummy Host Bridge |
| 146 | device pci 1.1 on end # Bridge to PCIe Ethernet chip |
| 147 | device pci 8.0 on end # Dummy Host Bridge |
| 148 | device pci 8.1 on # Bridge to Bus A |
| 149 | device pci 0.0 on end # Internal GPU |
| 150 | device pci 0.1 on end # Display HDA |
| 151 | device pci 0.2 on end # Crypto Coprocessor |
| 152 | device pci 0.3 on end # USB 3.1 |
| 153 | device pci 0.4 off end # USB 3.1 |
| 154 | device pci 0.5 on end # Audio |
| 155 | device pci 0.6 on end # HDA |
| 156 | device pci 0.7 on end # non-Sensor Fusion Hub device |
| 157 | end |
| 158 | device pci 8.2 on # Bridge to Bus B |
| 159 | device pci 0.0 off end # AHCI |
| 160 | device pci 0.1 off end # integrated Ethernet MAC |
| 161 | device pci 0.2 off end # integrated Ethernet MAC |
| 162 | end |
| 163 | device pci 14.0 on end # SMBus |
| 164 | device pci 14.3 on # D14F3 bridge |
| 165 | chip superio/smsc/sio1036 # optional debug card |
| 166 | end |
| 167 | end |
| 168 | device pci 14.6 off end # SDHCI |
| 169 | device pci 18.0 on end # Data fabric [0-7] |
| 170 | device pci 18.1 on end |
| 171 | device pci 18.2 on end |
| 172 | device pci 18.3 on end |
| 173 | device pci 18.4 on end |
| 174 | device pci 18.5 on end |
| 175 | device pci 18.6 on end |
| 176 | device pci 18.7 on end |
| 177 | end # domain |
| 178 | |
| 179 | device mmio 0xfedc9000 on end # UART0 |
| 180 | device mmio 0xfedca000 on end # UART1 |
| 181 | device mmio 0xfedce000 off end # UART2 |
| 182 | device mmio 0xfedcf000 off end # UART3 |
| 183 | |
| 184 | end # chip soc/amd/picasso |