Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 2 | |
| 3 | #include <stdint.h> |
Kyösti Mälkki | 520717d | 2019-12-15 21:37:48 +0200 | [diff] [blame] | 4 | #include <arch/bootblock.h> |
| 5 | #include <amdblocks/acpimmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Kyösti Mälkki | 520717d | 2019-12-15 21:37:48 +0200 | [diff] [blame] | 7 | #include <southbridge/amd/pi/hudson/hudson.h> |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 8 | |
| 9 | /* |
| 10 | * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. |
| 11 | * |
| 12 | * Hardware should enable LPC ROM by pin straps. This function does not |
| 13 | * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. |
| 14 | * |
| 15 | * The HUDSON power-on default is to map 512K ROM space. |
| 16 | * |
| 17 | */ |
| 18 | static void hudson_enable_rom(void) |
| 19 | { |
| 20 | u8 reg8; |
Elyes HAOUAS | 2f58a00 | 2020-04-22 16:07:39 +0200 | [diff] [blame] | 21 | const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 22 | |
| 23 | /* Decode variable LPC ROM address ranges 1 and 2. */ |
Kyösti Mälkki | 282717e | 2019-12-09 08:08:58 +0200 | [diff] [blame] | 24 | reg8 = pci_s_read_config8(dev, 0x48); |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 25 | reg8 |= (1 << 3) | (1 << 4); |
Kyösti Mälkki | 282717e | 2019-12-09 08:08:58 +0200 | [diff] [blame] | 26 | pci_s_write_config8(dev, 0x48, reg8); |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 27 | |
| 28 | /* LPC ROM address range 1: */ |
| 29 | /* Enable LPC ROM range mirroring start at 0x000e(0000). */ |
Kyösti Mälkki | 282717e | 2019-12-09 08:08:58 +0200 | [diff] [blame] | 30 | pci_s_write_config16(dev, 0x68, 0x000e); |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 31 | /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ |
Kyösti Mälkki | 282717e | 2019-12-09 08:08:58 +0200 | [diff] [blame] | 32 | pci_s_write_config16(dev, 0x6a, 0x000f); |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 33 | |
| 34 | /* LPC ROM address range 2: */ |
| 35 | /* |
| 36 | * Enable LPC ROM range start at: |
| 37 | * 0xfff8(0000): 512KB |
| 38 | * 0xfff0(0000): 1MB |
| 39 | * 0xffe0(0000): 2MB |
| 40 | * 0xffc0(0000): 4MB |
| 41 | */ |
Kyösti Mälkki | 282717e | 2019-12-09 08:08:58 +0200 | [diff] [blame] | 42 | pci_s_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 43 | /* Enable LPC ROM range end at 0xffff(ffff). */ |
Kyösti Mälkki | 282717e | 2019-12-09 08:08:58 +0200 | [diff] [blame] | 44 | pci_s_write_config16(dev, 0x6e, 0xffff); |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 45 | } |
| 46 | |
Kyösti Mälkki | 520717d | 2019-12-15 21:37:48 +0200 | [diff] [blame] | 47 | void bootblock_early_southbridge_init(void) |
Michał Żygowski | 8cee45c | 2019-11-23 18:03:46 +0100 | [diff] [blame] | 48 | { |
Michał Żygowski | 8cee45c | 2019-11-23 18:03:46 +0100 | [diff] [blame] | 49 | u32 data; |
| 50 | |
Kyösti Mälkki | 520717d | 2019-12-15 21:37:48 +0200 | [diff] [blame] | 51 | hudson_enable_rom(); |
Felix Held | 70d1c72 | 2021-04-09 22:22:09 +0200 | [diff] [blame] | 52 | enable_acpimmio_decode_pm04(); |
Kyösti Mälkki | a244d5e | 2019-12-09 08:08:58 +0200 | [diff] [blame] | 53 | hudson_lpc_decode(); |
Michał Żygowski | 8cee45c | 2019-11-23 18:03:46 +0100 | [diff] [blame] | 54 | |
Kyösti Mälkki | 657d68b | 2019-12-03 12:36:09 +0200 | [diff] [blame] | 55 | if (CONFIG(POST_DEVICE_PCI_PCIE)) |
| 56 | hudson_pci_port80(); |
| 57 | else if (CONFIG(POST_DEVICE_LPC)) |
| 58 | hudson_lpc_port80(); |
| 59 | |
Elyes HAOUAS | 2f58a00 | 2020-04-22 16:07:39 +0200 | [diff] [blame] | 60 | const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); |
Michał Żygowski | 8cee45c | 2019-11-23 18:03:46 +0100 | [diff] [blame] | 61 | data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); |
| 62 | /* enable 0x2e/0x4e IO decoding for SuperIO */ |
| 63 | pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); |
| 64 | |
| 65 | /* |
| 66 | * Enable FCH to decode TPM associated Memory and IO regions for vboot |
| 67 | * |
| 68 | * Enable decoding of TPM cycles defined in TPM 1.2 spec |
| 69 | * Enable decoding of legacy TPM addresses: IO addresses 0x7f- |
| 70 | * 0x7e and 0xef-0xee. |
| 71 | */ |
| 72 | |
| 73 | data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE); |
| 74 | data |= TPM_12_EN | TPM_LEGACY_EN; |
| 75 | pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data); |
| 76 | |
| 77 | /* |
| 78 | * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for |
| 79 | * LpcClk[1:0]". This following register setting has been |
| 80 | * replicated in every reference design since Parmer, so it is |
| 81 | * believed to be required even though it is not documented in |
| 82 | * the SoC BKDGs. Without this setting, there is no serial |
| 83 | * output. |
| 84 | */ |
| 85 | pm_write8(0xd2, 0); |
| 86 | } |