Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 2 | |
Felix Held | 4b2464f | 2022-02-23 17:54:20 +0100 | [diff] [blame] | 3 | #include <arch/hpet.h> /* Include this before OEM.h to have HPET_BASE_ADDRESS from arch/x86 */ |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 4 | #include "SBPLATFORM.h" |
| 5 | #include "cfg.h" |
Elyes HAOUAS | 19f5ba8 | 2018-10-14 14:52:06 +0200 | [diff] [blame] | 6 | #include <OEM.h> |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 7 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 8 | #include <acpi/acpi.h> |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 9 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 10 | /** |
| 11 | * @brief South Bridge CIMx configuration |
| 12 | * |
Martin Roth | 3c3a50c | 2014-12-16 20:50:26 -0700 | [diff] [blame] | 13 | * should be called before executing CIMx functions. |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 14 | * this function will be called in romstage and ramstage. |
| 15 | */ |
| 16 | void sb800_cimx_config(AMDSBCFG *sb_config) |
| 17 | { |
Ronald G. Minnich | 2fc0a1d | 2014-10-18 11:19:28 +0000 | [diff] [blame] | 18 | uint16_t bios_size = BIOS_SIZE; |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 19 | if (!sb_config) |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 20 | return; |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 21 | |
Kyösti Mälkki | 78c5d58 | 2015-01-09 23:48:47 +0200 | [diff] [blame] | 22 | sb_config->S3Resume = acpi_is_wakeup_s3(); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 23 | |
| 24 | /* header */ |
| 25 | sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS; |
| 26 | |
| 27 | /* static Build Parameters */ |
Ronald G. Minnich | 2fc0a1d | 2014-10-18 11:19:28 +0000 | [diff] [blame] | 28 | sb_config->BuildParameters.BiosSize = bios_size; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 29 | sb_config->BuildParameters.LegacyFree = LEGACY_FREE; |
| 30 | sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; |
| 31 | sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; |
| 32 | sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; |
| 33 | sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; |
| 34 | sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; |
| 35 | sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; |
| 36 | sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; |
Kerry She | 6209c82 | 2011-08-18 18:44:00 +0800 | [diff] [blame] | 37 | sb_config->BuildParameters.SioHwmBaseAddress = SIO_HWM_BASE_ADDRESS; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 38 | sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; |
| 39 | sb_config->BuildParameters.GecShadowRomBase = GEC_BASE_ADDRESS; |
| 40 | sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; |
| 41 | sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; |
| 42 | sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID; |
| 43 | sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID; |
| 44 | sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID; |
| 45 | sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID; |
| 46 | sb_config->BuildParameters.OhciSsid = OHCI_SSID; |
| 47 | sb_config->BuildParameters.EhciSsid = EHCI_SSID; |
| 48 | sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID; |
| 49 | sb_config->BuildParameters.SmbusSsid = SMBUS_SSID; |
| 50 | sb_config->BuildParameters.IdeSsid = IDE_SSID; |
| 51 | sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID; |
| 52 | sb_config->BuildParameters.LpcSsid = LPC_SSID; |
| 53 | sb_config->BuildParameters.PCIBSsid = PCIB_SSID; |
| 54 | sb_config->BuildParameters.SpreadSpectrumType = Spread_Spectrum_Type; |
| 55 | sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS; |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 56 | sb_config->BuildParameters.ImcEnableOverWrite = IMC_ENABLE_OVER_WRITE; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 57 | |
| 58 | /* General */ |
| 59 | sb_config->SpreadSpectrum = SPREAD_SPECTRUM; |
| 60 | sb_config->PciClks = PCI_CLOCK_CTRL; |
| 61 | sb_config->HpetTimer = HPET_TIMER; |
Edward O'Callaghan | 691ff08 | 2014-08-03 19:42:02 +1000 | [diff] [blame] | 62 | sb_config->SbSpiSpeedSupport = 1; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 63 | |
| 64 | /* USB */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 65 | sb_config->USBMODE.UsbModeReg = USB_CONFIG; |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 66 | sb_config->SbUsbPll = 0; |
Edward O'Callaghan | 691ff08 | 2014-08-03 19:42:02 +1000 | [diff] [blame] | 67 | /* CG PLL multiplier for USB Rx 1.1 mode (0=disable, 1=enable) */ |
Tobias Diedrich | 0dab6d1 | 2015-06-15 01:59:03 +0200 | [diff] [blame] | 68 | sb_config->UsbRxMode = USB_RX_MODE; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 69 | |
| 70 | /* SATA */ |
| 71 | sb_config->SataClass = SATA_MODE; |
| 72 | sb_config->SataIdeMode = SATA_IDE_MODE; |
| 73 | sb_config->SataPortMultCap = SATA_PORT_MULT_CAP_RESERVED; |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 74 | sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 75 | sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. |
| 76 | //TODO: set to secondary not take effect. |
Kerry Sheh | d7e856b9 | 2011-10-11 17:27:06 +0800 | [diff] [blame] | 77 | sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CONFIG_IDE_COMBINED_MODE; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 78 | sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE; |
| 79 | |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 80 | /* Azalia HDA */ |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 81 | sb_config->AzaliaController = AZALIA_CONTROLLER; |
| 82 | sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG; |
| 83 | sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_SDIN_PIN; |
Elyes HAOUAS | e29c70d | 2019-12-30 15:20:13 +0100 | [diff] [blame] | 84 | /* Mainboard Specific Azalia Codec Verb Table */ |
Marc Jones | f154c01 | 2011-12-14 11:24:00 -0700 | [diff] [blame] | 85 | #ifdef AZALIA_OEM_VERB_TABLE |
| 86 | sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = (CODECTBLLIST *)AZALIA_OEM_VERB_TABLE; |
| 87 | #else |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 88 | sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL; |
Marc Jones | f154c01 | 2011-12-14 11:24:00 -0700 | [diff] [blame] | 89 | #endif |
Kerry She | 6209c82 | 2011-08-18 18:44:00 +0800 | [diff] [blame] | 90 | /* LPC */ |
| 91 | /* SuperIO hardware monitor register access */ |
Julius Werner | 5d1f9a0 | 2019-03-07 17:07:26 -0800 | [diff] [blame] | 92 | sb_config->SioHwmPortEnable = CONFIG(SB_SUPERIO_HWM); |
Kerry She | 6209c82 | 2011-08-18 18:44:00 +0800 | [diff] [blame] | 93 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 94 | /* |
| 95 | * GPP. default configure only enable port0 with 4 lanes, |
| 96 | * configure in devicetree.cb would overwrite the default configuration |
| 97 | */ |
| 98 | sb_config->GppFunctionEnable = GPP_CONTROLLER; |
| 99 | sb_config->GppLinkConfig = GPP_CFGMODE; |
| 100 | //sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = TRUE; |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 101 | sb_config->PORTCONFIG[0].PortCfg.PortPresent = CIMX_OPTION_ENABLED; |
| 102 | sb_config->PORTCONFIG[1].PortCfg.PortPresent = CIMX_OPTION_ENABLED; |
| 103 | sb_config->PORTCONFIG[2].PortCfg.PortPresent = CIMX_OPTION_ENABLED; |
| 104 | sb_config->PORTCONFIG[3].PortCfg.PortPresent = CIMX_OPTION_ENABLED; |
Kerry Sheh | f3b0500 | 2011-10-12 12:06:23 +0800 | [diff] [blame] | 105 | sb_config->GppUnhidePorts = SB_GPP_UNHIDE_PORTS; |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 106 | sb_config->NbSbGen2 = NB_SB_GEN2; |
| 107 | sb_config->GppGen2 = SB_GPP_GEN2; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 108 | |
| 109 | //cimx BTS fix |
| 110 | sb_config->GppMemWrImprove = TRUE; |
| 111 | sb_config->SbPcieOrderRule = TRUE; |
| 112 | sb_config->AlinkPhyPllPowerDown = TRUE; |
| 113 | sb_config->GppPhyPllPowerDown = TRUE; //GPP power saving |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 114 | sb_config->SBGecPwr = 0x03;//11b << 5, rpr BDF: 00:20:06 |
| 115 | sb_config->GecConfig = GEC_CONFIG; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 116 | } |