Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
WANG Siyuan | 55f9a73 | 2013-12-02 10:18:04 +0800 | [diff] [blame] | 2 | |
| 3 | #include "imc.h" |
Michał Żygowski | 287ce5f | 2019-12-01 17:41:23 +0100 | [diff] [blame] | 4 | #include <amdblocks/acpimmio.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 5 | #include <device/mmio.h> |
Elyes HAOUAS | 19f5ba8 | 2018-10-14 14:52:06 +0200 | [diff] [blame] | 6 | #include <Porting.h> |
| 7 | #include <AGESA.h> |
Kyösti Mälkki | 08311f5 | 2016-04-19 07:17:59 +0300 | [diff] [blame] | 8 | #include <amdlib.h> |
Alexandru Gagniuc | 01e0adf | 2014-03-29 17:07:26 -0500 | [diff] [blame] | 9 | #include <Proc/Fch/Fch.h> |
| 10 | #include <Proc/Fch/Common/FchCommonCfg.h> |
| 11 | #include <Proc/Fch/FchPlatform.h> |
WANG Siyuan | 55f9a73 | 2013-12-02 10:18:04 +0800 | [diff] [blame] | 12 | |
| 13 | void imc_reg_init(void) |
| 14 | { |
| 15 | /* Init Power Management Block 2 (PM2) Registers. |
| 16 | * Check BKDG for AMD Family 16h for details. */ |
Michał Żygowski | 287ce5f | 2019-12-01 17:41:23 +0100 | [diff] [blame] | 17 | pm2_write8(0, 0x06); |
| 18 | pm2_write8(1, 0x06); |
| 19 | pm2_write8(2, 0xf7); |
| 20 | pm2_write8(3, 0xff); |
| 21 | pm2_write8(4, 0xff); |
WANG Siyuan | 55f9a73 | 2013-12-02 10:18:04 +0800 | [diff] [blame] | 22 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 23 | #if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) |
Michał Żygowski | 287ce5f | 2019-12-01 17:41:23 +0100 | [diff] [blame] | 24 | pm2_write8(0x10, 0x06); |
| 25 | pm2_write8(0x11, 0x06); |
| 26 | pm2_write8(0x12, 0xf7); |
| 27 | pm2_write8(0x13, 0xff); |
| 28 | pm2_write8(0x14, 0xff); |
WANG Siyuan | 55f9a73 | 2013-12-02 10:18:04 +0800 | [diff] [blame] | 29 | #endif |
| 30 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 31 | #if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) |
WANG Siyuan | 55f9a73 | 2013-12-02 10:18:04 +0800 | [diff] [blame] | 32 | UINT8 PciData; |
| 33 | PCI_ADDR PciAddress; |
| 34 | AMD_CONFIG_PARAMS StdHeader; |
| 35 | PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 0x3, 0x1E4); |
| 36 | LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader); |
| 37 | PciData &= (UINT8)0x8F; |
| 38 | PciData |= 0x10; |
| 39 | LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader); |
| 40 | #endif |
| 41 | } |
| 42 | |
WANG Siyuan | 55f9a73 | 2013-12-02 10:18:04 +0800 | [diff] [blame] | 43 | void enable_imc_thermal_zone(void) |
| 44 | { |
| 45 | AMD_CONFIG_PARAMS StdHeader; |
| 46 | UINT8 FunNum; |
Richard Spiegel | 4195b10 | 2017-11-28 06:54:02 -0700 | [diff] [blame] | 47 | UINT8 regs[10]; |
WANG Siyuan | 55f9a73 | 2013-12-02 10:18:04 +0800 | [diff] [blame] | 48 | int i; |
| 49 | |
| 50 | regs[0] = 0; |
| 51 | regs[1] = 0; |
| 52 | FunNum = Fun_80; |
Elyes HAOUAS | c021ffe | 2016-09-18 19:18:56 +0200 | [diff] [blame] | 53 | for (i = 0; i <= 1; i++) |
WANG Siyuan | 55f9a73 | 2013-12-02 10:18:04 +0800 | [diff] [blame] | 54 | WriteECmsg(MSG_REG0 + i, AccessWidth8, ®s[i], &StdHeader); |
| 55 | WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number |
| 56 | WaitForEcLDN9MailboxCmdAck(&StdHeader); |
| 57 | |
Richard Spiegel | 4195b10 | 2017-11-28 06:54:02 -0700 | [diff] [blame] | 58 | for (i = 2; i < ARRAY_SIZE(regs); i++) |
WANG Siyuan | 55f9a73 | 2013-12-02 10:18:04 +0800 | [diff] [blame] | 59 | ReadECmsg(MSG_REG0 + i, AccessWidth8, ®s[i], &StdHeader); |
| 60 | |
| 61 | /* enable thermal zone 0 */ |
| 62 | regs[2] |= 1; |
| 63 | regs[0] = 0; |
| 64 | regs[1] = 0; |
| 65 | FunNum = Fun_81; |
Richard Spiegel | 4195b10 | 2017-11-28 06:54:02 -0700 | [diff] [blame] | 66 | for (i = 0; i < ARRAY_SIZE(regs); i++) |
WANG Siyuan | 55f9a73 | 2013-12-02 10:18:04 +0800 | [diff] [blame] | 67 | WriteECmsg(MSG_REG0 + i, AccessWidth8, ®s[i], &StdHeader); |
| 68 | WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number |
| 69 | WaitForEcLDN9MailboxCmdAck(&StdHeader); |
| 70 | } |