Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 2 | |
| 3 | #ifndef HUDSON_H |
| 4 | #define HUDSON_H |
| 5 | |
Zheng Bao | 7b4a99c | 2013-11-05 13:58:50 +0800 | [diff] [blame] | 6 | #include <device/device.h> |
Elyes HAOUAS | 07b7fc1 | 2020-07-22 11:47:55 +0200 | [diff] [blame] | 7 | #include <types.h> |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 8 | |
| 9 | /* Power management index/data registers */ |
| 10 | #define BIOSRAM_INDEX 0xcd4 |
| 11 | #define BIOSRAM_DATA 0xcd5 |
| 12 | #define PM_INDEX 0xcd6 |
| 13 | #define PM_DATA 0xcd7 |
Alexandru Gagniuc | 288c958 | 2014-04-14 16:35:34 -0500 | [diff] [blame] | 14 | #define PM2_INDEX 0xcd0 |
| 15 | #define PM2_DATA 0xcd1 |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 16 | |
| 17 | #define HUDSON_ACPI_IO_BASE 0x800 |
| 18 | |
| 19 | #define ACPI_PM_EVT_BLK (HUDSON_ACPI_IO_BASE + 0x00) /* 4 bytes */ |
| 20 | #define ACPI_PM1_CNT_BLK (HUDSON_ACPI_IO_BASE + 0x04) /* 2 bytes */ |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 21 | #define ACPI_PM_TMR_BLK (HUDSON_ACPI_IO_BASE + 0x18) /* 4 bytes */ |
| 22 | #define ACPI_GPE0_BLK (HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */ |
| 23 | #define ACPI_CPU_CONTROL (HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */ |
| 24 | |
Alexandru Gagniuc | 288c958 | 2014-04-14 16:35:34 -0500 | [diff] [blame] | 25 | #define ACPI_SMI_CTL_PORT 0xb2 |
| 26 | #define ACPI_SMI_CMD_CST_CONTROL 0xde |
| 27 | #define ACPI_SMI_CMD_PST_CONTROL 0xad |
| 28 | #define ACPI_SMI_CMD_DISABLE 0xbe |
| 29 | #define ACPI_SMI_CMD_ENABLE 0xef |
| 30 | #define ACPI_SMI_CMD_S4_REQ 0xc0 |
| 31 | |
Alexandru Gagniuc | cf1f9b6 | 2014-04-20 13:24:42 -0500 | [diff] [blame] | 32 | #define REV_HUDSON_A11 0x11 |
| 33 | #define REV_HUDSON_A12 0x12 |
| 34 | |
Michał Żygowski | 8cee45c | 2019-11-23 18:03:46 +0100 | [diff] [blame] | 35 | #define LPC_IO_PORT_DECODE_ENABLE 0x44 |
| 36 | #define DECODE_ENABLE_PARALLEL_PORT0 BIT(0) |
| 37 | #define DECODE_ENABLE_PARALLEL_PORT1 BIT(1) |
| 38 | #define DECODE_ENABLE_PARALLEL_PORT2 BIT(2) |
| 39 | #define DECODE_ENABLE_PARALLEL_PORT3 BIT(3) |
| 40 | #define DECODE_ENABLE_PARALLEL_PORT4 BIT(4) |
| 41 | #define DECODE_ENABLE_PARALLEL_PORT5 BIT(5) |
| 42 | #define DECODE_ENABLE_SERIAL_PORT0 BIT(6) |
| 43 | #define DECODE_ENABLE_SERIAL_PORT1 BIT(7) |
| 44 | #define DECODE_ENABLE_SERIAL_PORT2 BIT(8) |
| 45 | #define DECODE_ENABLE_SERIAL_PORT3 BIT(9) |
| 46 | #define DECODE_ENABLE_SERIAL_PORT4 BIT(10) |
| 47 | #define DECODE_ENABLE_SERIAL_PORT5 BIT(11) |
| 48 | #define DECODE_ENABLE_SERIAL_PORT6 BIT(12) |
| 49 | #define DECODE_ENABLE_SERIAL_PORT7 BIT(13) |
| 50 | #define DECODE_ENABLE_AUDIO_PORT0 BIT(14) |
| 51 | #define DECODE_ENABLE_AUDIO_PORT1 BIT(15) |
| 52 | #define DECODE_ENABLE_AUDIO_PORT2 BIT(16) |
| 53 | #define DECODE_ENABLE_AUDIO_PORT3 BIT(17) |
| 54 | #define DECODE_ENABLE_MIDI_PORT0 BIT(18) |
| 55 | #define DECODE_ENABLE_MIDI_PORT1 BIT(19) |
| 56 | #define DECODE_ENABLE_MIDI_PORT2 BIT(20) |
| 57 | #define DECODE_ENABLE_MIDI_PORT3 BIT(21) |
| 58 | #define DECODE_ENABLE_MSS_PORT0 BIT(22) |
| 59 | #define DECODE_ENABLE_MSS_PORT1 BIT(23) |
| 60 | #define DECODE_ENABLE_MSS_PORT2 BIT(24) |
| 61 | #define DECODE_ENABLE_MSS_PORT3 BIT(25) |
| 62 | #define DECODE_ENABLE_FDC_PORT0 BIT(26) |
| 63 | #define DECODE_ENABLE_FDC_PORT1 BIT(27) |
| 64 | #define DECODE_ENABLE_GAME_PORT BIT(28) |
| 65 | #define DECODE_ENABLE_KBC_PORT BIT(29) |
| 66 | #define DECODE_ENABLE_ACPIUC_PORT BIT(30) |
| 67 | #define DECODE_ENABLE_ADLIB_PORT BIT(31) |
| 68 | |
| 69 | #define LPC_IO_OR_MEM_DECODE_ENABLE 0x48 |
| 70 | |
| 71 | #define LPC_TRUSTED_PLATFORM_MODULE 0x7c |
| 72 | #define TPM_12_EN BIT(0) |
| 73 | #define TPM_LEGACY_EN BIT(2) |
| 74 | |
Dave Frodin | ac1b875 | 2014-06-05 14:30:22 -0600 | [diff] [blame] | 75 | #define SPIROM_BASE_ADDRESS_REGISTER 0xA0 |
| 76 | #define SPI_ROM_ENABLE 0x02 |
| 77 | #define SPI_BASE_ADDRESS 0xFEC10000 |
Alexandru Gagniuc | cf1f9b6 | 2014-04-20 13:24:42 -0500 | [diff] [blame] | 78 | |
Kyösti Mälkki | 84693d3 | 2014-11-14 20:56:43 +0200 | [diff] [blame] | 79 | static inline int hudson_sata_enable(void) |
| 80 | { |
| 81 | /* True if IDE or AHCI. */ |
| 82 | return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 2); |
| 83 | } |
| 84 | |
| 85 | static inline int hudson_ide_enable(void) |
| 86 | { |
| 87 | /* True if IDE or LEGACY IDE. */ |
| 88 | return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); |
| 89 | } |
| 90 | |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 91 | void hudson_lpc_port80(void); |
| 92 | void hudson_pci_port80(void); |
Michał Żygowski | 8cee45c | 2019-11-23 18:03:46 +0100 | [diff] [blame] | 93 | void hudson_lpc_decode(void); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 94 | void hudson_clk_output_48Mhz(void); |
| 95 | |
Elyes HAOUAS | a93e754 | 2018-05-19 14:30:47 +0200 | [diff] [blame] | 96 | void hudson_enable(struct device *dev); |
Zheng Bao | 7b4a99c | 2013-11-05 13:58:50 +0800 | [diff] [blame] | 97 | |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 98 | #endif /* HUDSON_H */ |