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review.coreboot.org / coreboot / 27d6299d51744bda549b7764b8fde909ad812e33 / . / src / soc / ti / am335x / sdram.h
blob: e76073fb2f7458e3cf95f62910e5adc44829eb08 [file] [log] [blame]
Sam Lewis1d8d99b2020-08-06 21:08:20 +1000[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#ifndef __CPU_TI_AM335X_DDR_INIT_H__
4#define __CPU_TI_AM335X_DDR_INIT_H__
5
6#include <types.h>
7
8struct ctrl_ioregs {
9 uint32_t cm0ioctl;
10 uint32_t cm1ioctl;
11 uint32_t cm2ioctl;
12 uint32_t dt0ioctl;
13 uint32_t dt1ioctl;
14 uint32_t dt2ioctrl;
15 uint32_t dt3ioctrl;
16 uint32_t emif_sdram_config_ext;
17};
18
19/**
20 * Encapsulates DDR DATA registers.
21 */
22struct ddr_data {
23 uint32_t datardsratio0;
24 uint32_t datawdsratio0;
25 uint32_t datawiratio0;
26 uint32_t datagiratio0;
27 uint32_t datafwsratio0;
28 uint32_t datawrsratio0;
29};
30
31/**
32 * Encapsulates DDR CMD control registers.
33 */
34struct cmd_control {
35 uint32_t cmd0csratio;
36 uint32_t cmd0csforce;
37 uint32_t cmd0csdelay;
38 uint32_t cmd0iclkout;
39 uint32_t cmd1csratio;
40 uint32_t cmd1csforce;
41 uint32_t cmd1csdelay;
42 uint32_t cmd1iclkout;
43 uint32_t cmd2csratio;
44 uint32_t cmd2csforce;
45 uint32_t cmd2csdelay;
46 uint32_t cmd2iclkout;
47};
48
49
50/*
51 * Structure containing shadow of important registers in EMIF
52 * The calculation function fills in this structure to be later used for
53 * initialization and DVFS
54 */
55struct emif_regs {
56 uint32_t freq;
57 uint32_t sdram_config_init;
58 uint32_t sdram_config;
59 uint32_t sdram_config2;
60 uint32_t ref_ctrl;
61 uint32_t ref_ctrl_final;
62 uint32_t sdram_tim1;
63 uint32_t sdram_tim2;
64 uint32_t sdram_tim3;
65 uint32_t ocp_config;
66 uint32_t read_idle_ctrl;
67 uint32_t zq_config;
68 uint32_t temp_alert_config;
69 uint32_t emif_ddr_phy_ctlr_1_init;
70 uint32_t emif_ddr_phy_ctlr_1;
71 uint32_t emif_ddr_ext_phy_ctrl_1;
72 uint32_t emif_ddr_ext_phy_ctrl_2;
73 uint32_t emif_ddr_ext_phy_ctrl_3;
74 uint32_t emif_ddr_ext_phy_ctrl_4;
75 uint32_t emif_ddr_ext_phy_ctrl_5;
76 uint32_t emif_rd_wr_lvl_rmp_win;
77 uint32_t emif_rd_wr_lvl_rmp_ctl;
78 uint32_t emif_rd_wr_lvl_ctl;
79 uint32_t emif_rd_wr_exec_thresh;
80 uint32_t emif_prio_class_serv_map;
81 uint32_t emif_connect_id_serv_1_map;
82 uint32_t emif_connect_id_serv_2_map;
83 uint32_t emif_cos_config;
84 uint32_t emif_ecc_ctrl_reg;
85 uint32_t emif_ecc_address_range_1;
86 uint32_t emif_ecc_address_range_2;
87};
88
89/* VTP Registers */
90struct vtp_reg {
91 uint32_t vtp0ctrlreg;
92};
93
94
95/* Reg mapping structure */
96struct emif_reg_struct {
97 uint32_t emif_mod_id_rev;
98 uint32_t emif_status;
99 uint32_t emif_sdram_config;
100 uint32_t emif_lpddr2_nvm_config;
101 uint32_t emif_sdram_ref_ctrl;
102 uint32_t emif_sdram_ref_ctrl_shdw;
103 uint32_t emif_sdram_tim_1;
104 uint32_t emif_sdram_tim_1_shdw;
105 uint32_t emif_sdram_tim_2;
106 uint32_t emif_sdram_tim_2_shdw;
107 uint32_t emif_sdram_tim_3;
108 uint32_t emif_sdram_tim_3_shdw;
109 uint32_t emif_lpddr2_nvm_tim;
110 uint32_t emif_lpddr2_nvm_tim_shdw;
111 uint32_t emif_pwr_mgmt_ctrl;
112 uint32_t emif_pwr_mgmt_ctrl_shdw;
113 uint32_t emif_lpddr2_mode_reg_data;
114 uint32_t padding1[1];
115 uint32_t emif_lpddr2_mode_reg_data_es2;
116 uint32_t padding11[1];
117 uint32_t emif_lpddr2_mode_reg_cfg;
118 uint32_t emif_l3_config;
119 uint32_t emif_l3_cfg_val_1;
120 uint32_t emif_l3_cfg_val_2;
121 uint32_t emif_iodft_tlgc;
122 uint32_t padding2[7];
123 uint32_t emif_perf_cnt_1;
124 uint32_t emif_perf_cnt_2;
125 uint32_t emif_perf_cnt_cfg;
126 uint32_t emif_perf_cnt_sel;
127 uint32_t emif_perf_cnt_tim;
128 uint32_t padding3;
129 uint32_t emif_read_idlectrl;
130 uint32_t emif_read_idlectrl_shdw;
131 uint32_t padding4;
132 uint32_t emif_irqstatus_raw_sys;
133 uint32_t emif_irqstatus_raw_ll;
134 uint32_t emif_irqstatus_sys;
135 uint32_t emif_irqstatus_ll;
136 uint32_t emif_irqenable_set_sys;
137 uint32_t emif_irqenable_set_ll;
138 uint32_t emif_irqenable_clr_sys;
139 uint32_t emif_irqenable_clr_ll;
140 uint32_t padding5;
141 uint32_t emif_zq_config;
142 uint32_t emif_temp_alert_config;
143 uint32_t emif_l3_err_log;
144 uint32_t emif_rd_wr_lvl_rmp_win;
145 uint32_t emif_rd_wr_lvl_rmp_ctl;
146 uint32_t emif_rd_wr_lvl_ctl;
147 uint32_t padding6[1];
148 uint32_t emif_ddr_phy_ctrl_1;
149 uint32_t emif_ddr_phy_ctrl_1_shdw;
150 uint32_t emif_ddr_phy_ctrl_2;
151 uint32_t padding7[4];
152 uint32_t emif_prio_class_serv_map;
153 uint32_t emif_connect_id_serv_1_map;
154 uint32_t emif_connect_id_serv_2_map;
155 uint32_t padding8;
156 uint32_t emif_ecc_ctrl_reg;
157 uint32_t emif_ecc_address_range_1;
158 uint32_t emif_ecc_address_range_2;
159 uint32_t padding8_1;
160 uint32_t emif_rd_wr_exec_thresh;
161 uint32_t emif_cos_config;
162 uint32_t padding9[6];
163 uint32_t emif_ddr_phy_status[28];
164 uint32_t padding10[20];
165 uint32_t emif_ddr_ext_phy_ctrl_1;
166 uint32_t emif_ddr_ext_phy_ctrl_1_shdw;
167 uint32_t emif_ddr_ext_phy_ctrl_2;
168 uint32_t emif_ddr_ext_phy_ctrl_2_shdw;
169 uint32_t emif_ddr_ext_phy_ctrl_3;
170 uint32_t emif_ddr_ext_phy_ctrl_3_shdw;
171 uint32_t emif_ddr_ext_phy_ctrl_4;
172 uint32_t emif_ddr_ext_phy_ctrl_4_shdw;
173 uint32_t emif_ddr_ext_phy_ctrl_5;
174 uint32_t emif_ddr_ext_phy_ctrl_5_shdw;
175 uint32_t emif_ddr_ext_phy_ctrl_6;
176 uint32_t emif_ddr_ext_phy_ctrl_6_shdw;
177 uint32_t emif_ddr_ext_phy_ctrl_7;
178 uint32_t emif_ddr_ext_phy_ctrl_7_shdw;
179 uint32_t emif_ddr_ext_phy_ctrl_8;
180 uint32_t emif_ddr_ext_phy_ctrl_8_shdw;
181 uint32_t emif_ddr_ext_phy_ctrl_9;
182 uint32_t emif_ddr_ext_phy_ctrl_9_shdw;
183 uint32_t emif_ddr_ext_phy_ctrl_10;
184 uint32_t emif_ddr_ext_phy_ctrl_10_shdw;
185 uint32_t emif_ddr_ext_phy_ctrl_11;
186 uint32_t emif_ddr_ext_phy_ctrl_11_shdw;
187 uint32_t emif_ddr_ext_phy_ctrl_12;
188 uint32_t emif_ddr_ext_phy_ctrl_12_shdw;
189 uint32_t emif_ddr_ext_phy_ctrl_13;
190 uint32_t emif_ddr_ext_phy_ctrl_13_shdw;
191 uint32_t emif_ddr_ext_phy_ctrl_14;
192 uint32_t emif_ddr_ext_phy_ctrl_14_shdw;
193 uint32_t emif_ddr_ext_phy_ctrl_15;
194 uint32_t emif_ddr_ext_phy_ctrl_15_shdw;
195 uint32_t emif_ddr_ext_phy_ctrl_16;
196 uint32_t emif_ddr_ext_phy_ctrl_16_shdw;
197 uint32_t emif_ddr_ext_phy_ctrl_17;
198 uint32_t emif_ddr_ext_phy_ctrl_17_shdw;
199 uint32_t emif_ddr_ext_phy_ctrl_18;
200 uint32_t emif_ddr_ext_phy_ctrl_18_shdw;
201 uint32_t emif_ddr_ext_phy_ctrl_19;
202 uint32_t emif_ddr_ext_phy_ctrl_19_shdw;
203 uint32_t emif_ddr_ext_phy_ctrl_20;
204 uint32_t emif_ddr_ext_phy_ctrl_20_shdw;
205 uint32_t emif_ddr_ext_phy_ctrl_21;
206 uint32_t emif_ddr_ext_phy_ctrl_21_shdw;
207 uint32_t emif_ddr_ext_phy_ctrl_22;
208 uint32_t emif_ddr_ext_phy_ctrl_22_shdw;
209 uint32_t emif_ddr_ext_phy_ctrl_23;
210 uint32_t emif_ddr_ext_phy_ctrl_23_shdw;
211 uint32_t emif_ddr_ext_phy_ctrl_24;
212 uint32_t emif_ddr_ext_phy_ctrl_24_shdw;
213 uint32_t emif_ddr_ext_phy_ctrl_25;
214 uint32_t emif_ddr_ext_phy_ctrl_25_shdw;
215 uint32_t emif_ddr_ext_phy_ctrl_26;
216 uint32_t emif_ddr_ext_phy_ctrl_26_shdw;
217 uint32_t emif_ddr_ext_phy_ctrl_27;
218 uint32_t emif_ddr_ext_phy_ctrl_27_shdw;
219 uint32_t emif_ddr_ext_phy_ctrl_28;
220 uint32_t emif_ddr_ext_phy_ctrl_28_shdw;
221 uint32_t emif_ddr_ext_phy_ctrl_29;
222 uint32_t emif_ddr_ext_phy_ctrl_29_shdw;
223 uint32_t emif_ddr_ext_phy_ctrl_30;
224 uint32_t emif_ddr_ext_phy_ctrl_30_shdw;
225 uint32_t emif_ddr_ext_phy_ctrl_31;
226 uint32_t emif_ddr_ext_phy_ctrl_31_shdw;
227 uint32_t emif_ddr_ext_phy_ctrl_32;
228 uint32_t emif_ddr_ext_phy_ctrl_32_shdw;
229 uint32_t emif_ddr_ext_phy_ctrl_33;
230 uint32_t emif_ddr_ext_phy_ctrl_33_shdw;
231 uint32_t emif_ddr_ext_phy_ctrl_34;
232 uint32_t emif_ddr_ext_phy_ctrl_34_shdw;
233 uint32_t emif_ddr_ext_phy_ctrl_35;
234 uint32_t emif_ddr_ext_phy_ctrl_35_shdw;
235 union {
236 uint32_t emif_ddr_ext_phy_ctrl_36;
237 uint32_t emif_ddr_fifo_misaligned_clear_1;
238 };
239 union {
240 uint32_t emif_ddr_ext_phy_ctrl_36_shdw;
241 uint32_t emif_ddr_fifo_misaligned_clear_2;
242 };
243};
244
245struct ddr_cmd_regs {
246 uint32_t resv0[7];
247 uint32_t cm0csratio; /* offset 0x01C */
248 uint32_t resv1[3];
249 uint32_t cm0iclkout; /* offset 0x02C */
250 uint32_t resv2[8];
251 uint32_t cm1csratio; /* offset 0x050 */
252 uint32_t resv3[3];
253 uint32_t cm1iclkout; /* offset 0x060 */
254 uint32_t resv4[8];
255 uint32_t cm2csratio; /* offset 0x084 */
256 uint32_t resv5[3];
257 uint32_t cm2iclkout; /* offset 0x094 */
258 uint32_t resv6[3];
259};
260
261struct ddr_data_regs {
262 uint32_t dt0rdsratio0; /* offset 0x0C8 */
263 uint32_t resv1[4];
264 uint32_t dt0wdsratio0; /* offset 0x0DC */
265 uint32_t resv2[4];
266 uint32_t dt0wiratio0; /* offset 0x0F0 */
267 uint32_t resv3;
268 uint32_t dt0wimode0; /* offset 0x0F8 */
269 uint32_t dt0giratio0; /* offset 0x0FC */
270 uint32_t resv4;
271 uint32_t dt0gimode0; /* offset 0x104 */
272 uint32_t dt0fwsratio0; /* offset 0x108 */
273 uint32_t resv5[4];
274 uint32_t dt0dqoffset; /* offset 0x11C */
275 uint32_t dt0wrsratio0; /* offset 0x120 */
276 uint32_t resv6[4];
277 uint32_t dt0rdelays0; /* offset 0x134 */
278 uint32_t dt0dldiff0; /* offset 0x138 */
279 uint32_t resv7[12];
280};
281
282/* Control Status Register */
283struct ctrl_stat {
284 uint32_t resv1[16];
285 uint32_t statusreg; /* ofset 0x40 */
286 uint32_t resv2[51];
287 uint32_t secure_emif_sdram_config; /* offset 0x0110 */
288 uint32_t resv3[319];
289 uint32_t dev_attr;
290};
291
292/**
293 * This structure represents the DDR io control on AM33XX devices.
294 */
295struct ddr_cmdtctrl {
296 uint32_t cm0ioctl;
297 uint32_t cm1ioctl;
298 uint32_t cm2ioctl;
299 uint32_t resv2[12];
300 uint32_t dt0ioctl;
301 uint32_t dt1ioctl;
302 uint32_t dt2ioctrl;
303 uint32_t dt3ioctrl;
304 uint32_t resv3[4];
305 uint32_t emif_sdram_config_ext;
306};
307
308struct ddr_ctrl {
309 uint32_t ddrioctrl;
310 uint32_t resv1[325];
311 uint32_t ddrckectrl;
312};
313
314/* AM335X EMIF Register values */
315#define VTP_CTRL_READY (0x1 << 5)
316#define VTP_CTRL_ENABLE (0x1 << 6)
317#define VTP_CTRL_START_EN (0x1)
318
319#define DDR_CKE_CTRL_NORMAL 0x1
320
321#define PHY_EN_DYN_PWRDN (0x1 << 20)
322
323/* VTP Base address */
324#define VTP0_CTRL_ADDR 0x44E10E0C
325#define VTP1_CTRL_ADDR 0x48140E10
326
327/* EMIF Base address */
328#define EMIF4_0_CFG_BASE 0x4C000000
329#define EMIF4_1_CFG_BASE 0x4D000000
330
331/* DDR Base address */
332#define DDR_PHY_CMD_ADDR 0x44E12000
333#define DDR_PHY_DATA_ADDR 0x44E120C8
334#define DDR_PHY_CMD_ADDR2 0x47C0C800
335#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
336#define DDR_DATA_REGS_NR 2
337
338/* DDR Base address */
339#define DDR_CTRL_ADDR 0x44E10E04
340#define DDR_CONTROL_BASE_ADDR 0x44E11404
341
342/* Control Module Base Address */
343#define CTRL_BASE 0x44E10000
344
345#define EMIF_REG_MAJOR_REVISION_SHIFT 8
346#define EMIF_REG_MAJOR_REVISION_MASK (0x7 << 8)
347
348#define EMIF_REG_SDRAM_TYPE_SHIFT 29
349#define EMIF_REG_SDRAM_TYPE_MASK (0x7 << 29)
350
351#define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5
352
353#define EMIF_REG_INITREF_DIS_MASK (1 << 31)
354#define EMIF_4D5 0x5
355
356/* SDRAM TYPE */
357#define EMIF_SDRAM_TYPE_DDR2 0x2
358#define EMIF_SDRAM_TYPE_DDR3 0x3
359#define EMIF_SDRAM_TYPE_LPDDR2 0x4
360
361#define PLL_BYPASS_MODE 0x4
362#define ST_MN_BYPASS 0x00000100
363#define ST_DPLL_CLK 0x00000001
364#define CLK_SEL_MASK 0x7ffff
365#define CLK_DIV_MASK 0x1f
366#define CLK_DIV2_MASK 0x7f
367#define CLK_SEL_SHIFT 0x8
368#define CLK_MODE_SEL 0x7
369#define CLK_MODE_MASK 0xfffffff8
370#define CLK_DIV_SEL 0xFFFFFFE0
371#define CPGMAC0_IDLE 0x30000
372#define DPLL_CLKDCOLDO_GATE_CTRL 0x300
373
374#define V_OSCK 24000000 /* Clock output from T2 */
375#define OSC (V_OSCK / 1000000)
376
377#define DDRPLL_M 266
378#define DDRPLL_N (OSC - 1)
379#define DDRPLL_M2 1
380
381void config_ddr(uint32_t pll, const struct ctrl_ioregs *ioregs, const struct ddr_data *data,
382 const struct cmd_control *ctrl, const struct emif_regs *regs, int nr);
383
384#endif