Patrick Georgi | afd4c87 | 2020-05-05 23:43:18 +0200 | [diff] [blame] | 1 | /* DDR3 mem setup file for EXYNOS5 based board */ |
Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 2 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 3 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 4 | #include <device/mmio.h> |
Julius Werner | 80af442 | 2014-10-20 13:18:56 -0700 | [diff] [blame] | 5 | #include <delay.h> |
| 6 | #include <soc/clk.h> |
| 7 | #include <soc/dmc.h> |
| 8 | #include <soc/power.h> |
| 9 | #include <soc/setup.h> |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 10 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 11 | #define TIMEOUT 10000 |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 12 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 13 | /* 'reset' field is currently ignored. */ |
| 14 | |
| 15 | int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 16 | { |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 17 | u32 val, nLockR, nLockW_phy0, nLockW_phy1; |
David Hendricks | 72a4288 | 2013-08-23 15:25:07 -0700 | [diff] [blame] | 18 | int i, chip; |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 19 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 20 | /* Enable PAUSE for DREX */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 21 | setbits32(&exynos_clock->pause, ENABLE_BIT); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 22 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 23 | /* Enable BYPASS mode */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 24 | setbits32(&exynos_clock->bpll_con1, BYPASS_EN); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 25 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 26 | write32(&exynos_clock->clk_src_cdrex, MUX_BPLL_SEL_FOUTBPLL); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 27 | do { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 28 | val = read32(&exynos_clock->clk_mux_stat_cdrex); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 29 | val &= BPLL_SEL_MASK; |
| 30 | } while (val != FOUTBPLL); |
| 31 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 32 | clrbits32(&exynos_clock->bpll_con1, BYPASS_EN); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 33 | |
| 34 | /* Specify the DDR memory type as DDR3 */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 35 | val = read32(&exynos_phy0_control->phy_con0); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 36 | val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); |
David Hendricks | 5a0fdb4 | 2013-08-29 13:12:56 -0700 | [diff] [blame] | 37 | val |= (mem->mem_type << PHY_CON0_CTRL_DDR_MODE_SHIFT); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 38 | write32(&exynos_phy0_control->phy_con0, val); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 39 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 40 | val = read32(&exynos_phy1_control->phy_con0); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 41 | val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); |
David Hendricks | 5a0fdb4 | 2013-08-29 13:12:56 -0700 | [diff] [blame] | 42 | val |= (mem->mem_type << PHY_CON0_CTRL_DDR_MODE_SHIFT); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 43 | write32(&exynos_phy1_control->phy_con0, val); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 44 | |
| 45 | /* Set Read Latency and Burst Length for PHY0 and PHY1 */ |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 46 | val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | |
| 47 | (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 48 | write32(&exynos_phy0_control->phy_con42, val); |
| 49 | write32(&exynos_phy1_control->phy_con42, val); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 50 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 51 | val = read32(&exynos_phy0_control->phy_con26); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 52 | val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET); |
| 53 | val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 54 | write32(&exynos_phy0_control->phy_con26, val); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 55 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 56 | val = read32(&exynos_phy1_control->phy_con26); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 57 | val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET); |
| 58 | val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 59 | write32(&exynos_phy1_control->phy_con26, val); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 60 | |
| 61 | /* Set Driver strength for CK, CKE, CS & CA to 0x7 |
| 62 | * Set Driver strength for Data Slice 0~3 to 0x6 |
| 63 | */ |
| 64 | val = (0x7 << CA_CK_DRVR_DS_OFFSET) | (0x7 << CA_CKE_DRVR_DS_OFFSET) | |
| 65 | (0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET); |
David Hendricks | 42b1b80 | 2013-08-26 15:12:12 -0700 | [diff] [blame] | 66 | val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) | |
| 67 | (0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 68 | write32(&exynos_phy0_control->phy_con39, val); |
| 69 | write32(&exynos_phy1_control->phy_con39, val); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 70 | |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 71 | /* ZQ Calibration */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 72 | if (dmc_config_zq(mem, exynos_phy0_control, exynos_phy1_control)) |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 73 | return SETUP_ERR_ZQ_CALIBRATION_FAILURE; |
| 74 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 75 | clrbits32(&exynos_phy0_control->phy_con16, ZQ_CLK_DIV_EN); |
| 76 | clrbits32(&exynos_phy1_control->phy_con16, ZQ_CLK_DIV_EN); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 77 | |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 78 | /* DQ Signal */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 79 | val = read32(&exynos_phy0_control->phy_con14); |
David Hendricks | 42b1b80 | 2013-08-26 15:12:12 -0700 | [diff] [blame] | 80 | val |= mem->phy0_pulld_dqs; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 81 | write32(&exynos_phy0_control->phy_con14, val); |
| 82 | val = read32(&exynos_phy1_control->phy_con14); |
David Hendricks | 42b1b80 | 2013-08-26 15:12:12 -0700 | [diff] [blame] | 83 | val |= mem->phy1_pulld_dqs; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 84 | write32(&exynos_phy1_control->phy_con14, val); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 85 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 86 | val = MEM_TERM_EN | PHY_TERM_EN; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 87 | write32(&exynos_drex0->phycontrol0, val); |
| 88 | write32(&exynos_drex1->phycontrol0, val); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 89 | |
Julius Werner | 9418476 | 2015-02-19 20:19:23 -0800 | [diff] [blame] | 90 | write32(&exynos_drex0->concontrol, mem->concontrol | |
| 91 | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | |
| 92 | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)); |
| 93 | write32(&exynos_drex1->concontrol, mem->concontrol | |
| 94 | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | |
| 95 | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 96 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 97 | do { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 98 | val = read32(&exynos_drex0->phystatus); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 99 | } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE); |
| 100 | do { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 101 | val = read32(&exynos_drex1->phystatus); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 102 | } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 103 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 104 | clrbits32(&exynos_drex0->concontrol, DFI_INIT_START); |
| 105 | clrbits32(&exynos_drex1->concontrol, DFI_INIT_START); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 106 | |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 107 | update_reset_dll(exynos_drex0, mem->mem_type); |
| 108 | update_reset_dll(exynos_drex1, mem->mem_type); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 109 | |
David Hendricks | 122b6d6 | 2013-08-29 14:05:21 -0700 | [diff] [blame] | 110 | /* MEMBASECONFIG0 (CS0) */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 111 | write32(&exynos_tzasc0->membaseconfig0, mem->membaseconfig0); |
| 112 | write32(&exynos_tzasc1->membaseconfig0, mem->membaseconfig0); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 113 | |
David Hendricks | 122b6d6 | 2013-08-29 14:05:21 -0700 | [diff] [blame] | 114 | /* MEMBASECONFIG1 (CS1) */ |
| 115 | if (mem->chips_per_channel == 2) { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 116 | write32(&exynos_tzasc0->membaseconfig1, mem->membaseconfig1); |
| 117 | write32(&exynos_tzasc1->membaseconfig1, mem->membaseconfig1); |
David Hendricks | 122b6d6 | 2013-08-29 14:05:21 -0700 | [diff] [blame] | 118 | } |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 119 | |
Martin Roth | 1fc2ba5 | 2014-12-07 14:59:11 -0700 | [diff] [blame] | 120 | /* Memory Channel Interleaving Size |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 121 | * Exynos5420 Channel interleaving = 128 bytes |
| 122 | */ |
| 123 | /* MEMCONFIG0/1 */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 124 | write32(&exynos_tzasc0->memconfig0, mem->memconfig); |
| 125 | write32(&exynos_tzasc1->memconfig0, mem->memconfig); |
| 126 | write32(&exynos_tzasc0->memconfig1, mem->memconfig); |
| 127 | write32(&exynos_tzasc1->memconfig1, mem->memconfig); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 128 | |
| 129 | /* Precharge Configuration */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 130 | write32(&exynos_drex0->prechconfig0, |
| 131 | mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT); |
| 132 | write32(&exynos_drex1->prechconfig0, |
| 133 | mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 134 | |
Martin Roth | 1fc2ba5 | 2014-12-07 14:59:11 -0700 | [diff] [blame] | 135 | /* TimingRow, TimingData, TimingPower and Timingref |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 136 | * values as per Memory AC parameters |
| 137 | */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 138 | write32(&exynos_drex0->timingref, mem->timing_ref); |
| 139 | write32(&exynos_drex1->timingref, mem->timing_ref); |
| 140 | write32(&exynos_drex0->timingrow, mem->timing_row); |
| 141 | write32(&exynos_drex1->timingrow, mem->timing_row); |
| 142 | write32(&exynos_drex0->timingdata, mem->timing_data); |
| 143 | write32(&exynos_drex1->timingdata, mem->timing_data); |
| 144 | write32(&exynos_drex0->timingpower, mem->timing_power); |
| 145 | write32(&exynos_drex1->timingpower, mem->timing_power); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 146 | |
Hung-Te Lin | c0491d4 | 2013-08-06 10:48:48 +0800 | [diff] [blame] | 147 | if (reset) { |
David Hendricks | 2f3dadd | 2013-08-20 17:13:01 -0700 | [diff] [blame] | 148 | /* Send NOP, MRS and ZQINIT commands. |
| 149 | * Sending MRS command will reset the DRAM. We should not be |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 150 | * resetting the DRAM after resume, this will lead to memory |
David Hendricks | 2f3dadd | 2013-08-20 17:13:01 -0700 | [diff] [blame] | 151 | * corruption as DRAM content is lost after DRAM reset. |
| 152 | */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 153 | dmc_config_mrs(mem, exynos_drex0); |
| 154 | dmc_config_mrs(mem, exynos_drex1); |
David Hendricks | 2f3dadd | 2013-08-20 17:13:01 -0700 | [diff] [blame] | 155 | } else { |
| 156 | u32 ret; |
| 157 | |
| 158 | /* |
| 159 | * During Suspend-Resume & S/W-Reset, as soon as PMU releases |
| 160 | * pad retention, CKE goes high. This causes memory contents |
Martin Roth | 1fc2ba5 | 2014-12-07 14:59:11 -0700 | [diff] [blame] | 161 | * not to be retained during DRAM initialization. Therefore, |
David Hendricks | 2f3dadd | 2013-08-20 17:13:01 -0700 | [diff] [blame] | 162 | * there is a new control register(0x100431e8[28]) which lets us |
| 163 | * release pad retention and retain the memory content until the |
| 164 | * initialization is complete. |
| 165 | */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 166 | write32(&exynos_power->padret_dram_cblk_opt, |
| 167 | PAD_RETENTION_DRAM_COREBLK_VAL); |
David Hendricks | 2f3dadd | 2013-08-20 17:13:01 -0700 | [diff] [blame] | 168 | do { |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 169 | ret = read32(&exynos_power->padret_dram_status); |
David Hendricks | 2f3dadd | 2013-08-20 17:13:01 -0700 | [diff] [blame] | 170 | } while (ret != 0x1); |
| 171 | |
| 172 | /* |
| 173 | * CKE PAD retention disables DRAM self-refresh mode. |
| 174 | * Send auto refresh command for DRAM refresh. |
| 175 | */ |
| 176 | for (i = 0; i < 128; i++) { |
David Hendricks | 72a4288 | 2013-08-23 15:25:07 -0700 | [diff] [blame] | 177 | for (chip = 0; chip < mem->chips_to_configure; chip++) { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 178 | write32(&exynos_drex0->directcmd, |
Julius Werner | 9418476 | 2015-02-19 20:19:23 -0800 | [diff] [blame] | 179 | DIRECT_CMD_REFA | |
| 180 | (chip << DIRECT_CMD_CHIP_SHIFT)); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 181 | write32(&exynos_drex1->directcmd, |
Julius Werner | 9418476 | 2015-02-19 20:19:23 -0800 | [diff] [blame] | 182 | DIRECT_CMD_REFA | |
| 183 | (chip << DIRECT_CMD_CHIP_SHIFT)); |
David Hendricks | 72a4288 | 2013-08-23 15:25:07 -0700 | [diff] [blame] | 184 | } |
David Hendricks | 2f3dadd | 2013-08-20 17:13:01 -0700 | [diff] [blame] | 185 | } |
Hung-Te Lin | c0491d4 | 2013-08-06 10:48:48 +0800 | [diff] [blame] | 186 | } |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 187 | |
| 188 | if (mem->gate_leveling_enable) { |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 189 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 190 | write32(&exynos_phy0_control->phy_con0, PHY_CON0_RESET_VAL); |
| 191 | write32(&exynos_phy1_control->phy_con0, PHY_CON0_RESET_VAL); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 192 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 193 | setbits32(&exynos_phy0_control->phy_con0, P0_CMD_EN); |
| 194 | setbits32(&exynos_phy1_control->phy_con0, P0_CMD_EN); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 195 | |
| 196 | val = PHY_CON2_RESET_VAL; |
| 197 | val |= INIT_DESKEW_EN; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 198 | write32(&exynos_phy0_control->phy_con2, val); |
| 199 | write32(&exynos_phy1_control->phy_con2, val); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 200 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 201 | val = read32(&exynos_phy0_control->phy_con1); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 202 | val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 203 | write32(&exynos_phy0_control->phy_con1, val); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 204 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 205 | val = read32(&exynos_phy1_control->phy_con1); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 206 | val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 207 | write32(&exynos_phy1_control->phy_con1, val); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 208 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 209 | nLockR = read32(&exynos_phy0_control->phy_con13); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 210 | nLockW_phy0 = (nLockR & CTRL_LOCK_COARSE_MASK) >> 2; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 211 | nLockR = read32(&exynos_phy0_control->phy_con12); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 212 | nLockR &= ~CTRL_DLL_ON; |
| 213 | nLockR |= nLockW_phy0; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 214 | write32(&exynos_phy0_control->phy_con12, nLockR); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 215 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 216 | nLockR = read32(&exynos_phy1_control->phy_con13); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 217 | nLockW_phy1 = (nLockR & CTRL_LOCK_COARSE_MASK) >> 2; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 218 | nLockR = read32(&exynos_phy1_control->phy_con12); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 219 | nLockR &= ~CTRL_DLL_ON; |
| 220 | nLockR |= nLockW_phy1; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 221 | write32(&exynos_phy1_control->phy_con12, nLockR); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 222 | |
David Hendricks | 0f0c720 | 2013-08-22 18:45:10 -0700 | [diff] [blame] | 223 | val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4; |
David Hendricks | 72a4288 | 2013-08-23 15:25:07 -0700 | [diff] [blame] | 224 | for (chip = 0; chip < mem->chips_to_configure; chip++) { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 225 | write32(&exynos_drex0->directcmd, |
| 226 | val | (chip << DIRECT_CMD_CHIP_SHIFT)); |
| 227 | write32(&exynos_drex1->directcmd, |
| 228 | val | (chip << DIRECT_CMD_CHIP_SHIFT)); |
David Hendricks | 72a4288 | 2013-08-23 15:25:07 -0700 | [diff] [blame] | 229 | } |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 230 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 231 | setbits32(&exynos_phy0_control->phy_con2, RDLVL_GATE_EN); |
| 232 | setbits32(&exynos_phy1_control->phy_con2, RDLVL_GATE_EN); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 233 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 234 | setbits32(&exynos_phy0_control->phy_con0, CTRL_SHGATE); |
| 235 | setbits32(&exynos_phy1_control->phy_con0, CTRL_SHGATE); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 236 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 237 | val = read32(&exynos_phy0_control->phy_con1); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 238 | val &= ~(CTRL_GATEDURADJ_MASK); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 239 | write32(&exynos_phy0_control->phy_con1, val); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 240 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 241 | val = read32(&exynos_phy1_control->phy_con1); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 242 | val &= ~(CTRL_GATEDURADJ_MASK); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 243 | write32(&exynos_phy1_control->phy_con1, val); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 244 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 245 | write32(&exynos_drex0->rdlvl_config, CTRL_RDLVL_GATE_ENABLE); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 246 | i = TIMEOUT; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 247 | while (((read32(&exynos_drex0->phystatus) & RDLVL_COMPLETE_CHO) |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 248 | != RDLVL_COMPLETE_CHO) && (i > 0)) { |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 249 | /* |
| 250 | * TODO(waihong): Comment on how long this take to |
| 251 | * timeout |
| 252 | */ |
| 253 | udelay(1); |
| 254 | i--; |
| 255 | } |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 256 | if (!i) |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 257 | return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 258 | write32(&exynos_drex0->rdlvl_config, CTRL_RDLVL_GATE_DISABLE); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 259 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 260 | write32(&exynos_drex1->rdlvl_config, CTRL_RDLVL_GATE_ENABLE); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 261 | i = TIMEOUT; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 262 | while (((read32(&exynos_drex1->phystatus) & RDLVL_COMPLETE_CHO) |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 263 | != RDLVL_COMPLETE_CHO) && (i > 0)) { |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 264 | /* |
| 265 | * TODO(waihong): Comment on how long this take to |
| 266 | * timeout |
| 267 | */ |
| 268 | udelay(1); |
| 269 | i--; |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 270 | } |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 271 | if (!i) |
| 272 | return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 273 | write32(&exynos_drex1->rdlvl_config, CTRL_RDLVL_GATE_DISABLE); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 274 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 275 | write32(&exynos_phy0_control->phy_con14, 0); |
| 276 | write32(&exynos_phy1_control->phy_con14, 0); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 277 | |
David Hendricks | 0f0c720 | 2013-08-22 18:45:10 -0700 | [diff] [blame] | 278 | val = (0x3 << DIRECT_CMD_BANK_SHIFT); |
David Hendricks | 72a4288 | 2013-08-23 15:25:07 -0700 | [diff] [blame] | 279 | for (chip = 0; chip < mem->chips_to_configure; chip++) { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 280 | write32(&exynos_drex0->directcmd, |
| 281 | val | (chip << DIRECT_CMD_CHIP_SHIFT)); |
| 282 | write32(&exynos_drex1->directcmd, |
| 283 | val | (chip << DIRECT_CMD_CHIP_SHIFT)); |
David Hendricks | 72a4288 | 2013-08-23 15:25:07 -0700 | [diff] [blame] | 284 | } |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 285 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 286 | /* Common Settings for Leveling */ |
| 287 | val = PHY_CON12_RESET_VAL; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 288 | write32(&exynos_phy0_control->phy_con12, (val + nLockW_phy0)); |
| 289 | write32(&exynos_phy1_control->phy_con12, (val + nLockW_phy1)); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 290 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 291 | setbits32(&exynos_phy0_control->phy_con2, DLL_DESKEW_EN); |
| 292 | setbits32(&exynos_phy1_control->phy_con2, DLL_DESKEW_EN); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 293 | } |
| 294 | |
| 295 | /* Send PALL command */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 296 | dmc_config_prech(mem, exynos_drex0); |
| 297 | dmc_config_prech(mem, exynos_drex1); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 298 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 299 | write32(&exynos_drex0->memcontrol, mem->memcontrol); |
| 300 | write32(&exynos_drex1->memcontrol, mem->memcontrol); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 301 | |
David Hendricks | 42b1b80 | 2013-08-26 15:12:12 -0700 | [diff] [blame] | 302 | /* |
| 303 | * Set DMC Concontrol: Enable auto-refresh counter, provide |
| 304 | * read data fetch cycles and enable DREX auto set powerdown |
| 305 | * for input buffer of I/O in none read memory state. |
| 306 | */ |
Julius Werner | 9418476 | 2015-02-19 20:19:23 -0800 | [diff] [blame] | 307 | write32(&exynos_drex0->concontrol, mem->concontrol | |
| 308 | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | |
| 309 | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | |
| 310 | DMC_CONCONTROL_IO_PD_CON(0x2)); |
| 311 | write32(&exynos_drex1->concontrol, mem->concontrol | |
| 312 | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | |
| 313 | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | |
| 314 | DMC_CONCONTROL_IO_PD_CON(0x2)); |
David Hendricks | b774313 | 2013-08-09 18:19:29 -0700 | [diff] [blame] | 315 | |
| 316 | /* Enable Clock Gating Control for DMC |
| 317 | * this saves around 25 mw dmc power as compared to the power |
| 318 | * consumption without these bits enabled |
| 319 | */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 320 | setbits32(&exynos_drex0->cgcontrol, DMC_INTERNAL_CG); |
| 321 | setbits32(&exynos_drex1->cgcontrol, DMC_INTERNAL_CG); |
David Hendricks | b774313 | 2013-08-09 18:19:29 -0700 | [diff] [blame] | 322 | |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 323 | return 0; |
| 324 | } |