Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Taniya Das | 0e03aa2 | 2019-08-07 11:28:28 +0530 | [diff] [blame] | 2 | |
| 3 | #include <assert.h> |
| 4 | #include <commonlib/helpers.h> |
| 5 | #include <device/mmio.h> |
| 6 | #include <soc/clock.h> |
| 7 | #include <types.h> |
| 8 | |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 9 | static struct clock_freq_config qspi_core_cfg[] = { |
Taniya Das | 0e03aa2 | 2019-08-07 11:28:28 +0530 | [diff] [blame] | 10 | { |
| 11 | .hz = SRC_XO_HZ, /* 19.2KHz */ |
| 12 | .src = SRC_XO_19_2MHZ, |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 13 | .div = QCOM_CLOCK_DIV(1), |
Taniya Das | 0e03aa2 | 2019-08-07 11:28:28 +0530 | [diff] [blame] | 14 | }, |
| 15 | { |
| 16 | .hz = 100 * MHz, |
| 17 | .src = SRC_GPLL0_EVEN_300MHZ, |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 18 | .div = QCOM_CLOCK_DIV(3), |
Taniya Das | 0e03aa2 | 2019-08-07 11:28:28 +0530 | [diff] [blame] | 19 | }, |
| 20 | { |
| 21 | .hz = 150 * MHz, |
| 22 | .src = SRC_GPLL0_EVEN_300MHZ, |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 23 | .div = QCOM_CLOCK_DIV(2), |
Taniya Das | 0e03aa2 | 2019-08-07 11:28:28 +0530 | [diff] [blame] | 24 | }, |
| 25 | { |
| 26 | .hz = GPLL0_EVEN_HZ, /* 300MHz */ |
| 27 | .src = SRC_GPLL0_EVEN_300MHZ, |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 28 | .div = QCOM_CLOCK_DIV(1), |
Taniya Das | 0e03aa2 | 2019-08-07 11:28:28 +0530 | [diff] [blame] | 29 | } |
| 30 | }; |
| 31 | |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 32 | static struct clock_freq_config qupv3_wrap_cfg[] = { |
Taniya Das | ece88ab | 2019-11-05 21:37:32 +0530 | [diff] [blame] | 33 | { |
| 34 | .hz = SRC_XO_HZ, /* 19.2KHz */ |
| 35 | .src = SRC_XO_19_2MHZ, |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 36 | .div = QCOM_CLOCK_DIV(1), |
Taniya Das | ece88ab | 2019-11-05 21:37:32 +0530 | [diff] [blame] | 37 | }, |
| 38 | { |
| 39 | .hz = 32 * MHz, |
| 40 | .src = SRC_GPLL0_EVEN_300MHZ, |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 41 | .div = QCOM_CLOCK_DIV(1), |
Taniya Das | ece88ab | 2019-11-05 21:37:32 +0530 | [diff] [blame] | 42 | .m = 8, |
| 43 | .n = 75, |
Taniya Das | 91dc1e7 | 2019-12-19 16:41:02 +0530 | [diff] [blame] | 44 | .d_2 = 75, |
Taniya Das | ece88ab | 2019-11-05 21:37:32 +0530 | [diff] [blame] | 45 | }, |
| 46 | { |
| 47 | .hz = 48 * MHz, |
| 48 | .src = SRC_GPLL0_EVEN_300MHZ, |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 49 | .div = QCOM_CLOCK_DIV(1), |
Taniya Das | ece88ab | 2019-11-05 21:37:32 +0530 | [diff] [blame] | 50 | .m = 4, |
| 51 | .n = 25, |
Taniya Das | 91dc1e7 | 2019-12-19 16:41:02 +0530 | [diff] [blame] | 52 | .d_2 = 25, |
Taniya Das | ece88ab | 2019-11-05 21:37:32 +0530 | [diff] [blame] | 53 | }, |
| 54 | { |
| 55 | .hz = 64 * MHz, |
| 56 | .src = SRC_GPLL0_EVEN_300MHZ, |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 57 | .div = QCOM_CLOCK_DIV(1), |
Taniya Das | ece88ab | 2019-11-05 21:37:32 +0530 | [diff] [blame] | 58 | .m = 16, |
| 59 | .n = 75, |
Taniya Das | 91dc1e7 | 2019-12-19 16:41:02 +0530 | [diff] [blame] | 60 | .d_2 = 75, |
Taniya Das | ece88ab | 2019-11-05 21:37:32 +0530 | [diff] [blame] | 61 | }, |
| 62 | { |
| 63 | .hz = 96 * MHz, |
| 64 | .src = SRC_GPLL0_EVEN_300MHZ, |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 65 | .div = QCOM_CLOCK_DIV(1), |
Taniya Das | ece88ab | 2019-11-05 21:37:32 +0530 | [diff] [blame] | 66 | .m = 8, |
| 67 | .n = 25, |
Taniya Das | 91dc1e7 | 2019-12-19 16:41:02 +0530 | [diff] [blame] | 68 | .d_2 = 25, |
Taniya Das | ece88ab | 2019-11-05 21:37:32 +0530 | [diff] [blame] | 69 | }, |
| 70 | { |
| 71 | .hz = 100 * MHz, |
| 72 | .src = SRC_GPLL0_EVEN_300MHZ, |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 73 | .div = QCOM_CLOCK_DIV(3), |
Taniya Das | ece88ab | 2019-11-05 21:37:32 +0530 | [diff] [blame] | 74 | }, |
| 75 | { |
| 76 | .hz = SRC_XO_HZ, /* 19.2KHz */ |
| 77 | .src = SRC_XO_19_2MHZ, |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 78 | .div = QCOM_CLOCK_DIV(1), |
Taniya Das | ece88ab | 2019-11-05 21:37:32 +0530 | [diff] [blame] | 79 | }, |
| 80 | { |
| 81 | .hz = SRC_XO_HZ, /* 19.2KHz */ |
| 82 | .src = SRC_XO_19_2MHZ, |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 83 | .div = QCOM_CLOCK_DIV(1), |
Taniya Das | ece88ab | 2019-11-05 21:37:32 +0530 | [diff] [blame] | 84 | }, |
| 85 | }; |
| 86 | |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 87 | static struct clock_rcg_mnd *mdss_clock[MDSS_CLK_COUNT] = { |
Taniya Das | dc92cea | 2019-07-08 12:00:51 +0530 | [diff] [blame] | 88 | [MDSS_CLK_ESC0] = &mdss->esc0, |
| 89 | [MDSS_CLK_PCLK0] = &mdss->pclk0, |
| 90 | [MDSS_CLK_BYTE0] = &mdss->byte0, |
| 91 | [MDSS_CLK_BYTE0_INTF] = &mdss->byte0, |
| 92 | }; |
| 93 | |
| 94 | static u32 *mdss_cbcr[MDSS_CLK_COUNT] = { |
| 95 | [MDSS_CLK_ESC0] = &mdss->esc0_cbcr, |
| 96 | [MDSS_CLK_PCLK0] = &mdss->pclk0_cbcr, |
| 97 | [MDSS_CLK_BYTE0] = &mdss->byte0_cbcr, |
| 98 | [MDSS_CLK_BYTE0_INTF] = &mdss->byte0_intf_cbcr, |
| 99 | }; |
| 100 | |
Taniya Das | 0e03aa2 | 2019-08-07 11:28:28 +0530 | [diff] [blame] | 101 | static int clock_configure_gpll0(void) |
| 102 | { |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 103 | struct alpha_pll_reg_val_config gpll0_cfg = {0}; |
Taniya Das | 0e03aa2 | 2019-08-07 11:28:28 +0530 | [diff] [blame] | 104 | |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 105 | gpll0_cfg.reg_user_ctl_hi = &gcc->gpll0.user_ctl_u; |
| 106 | gpll0_cfg.user_ctl_hi_val = 1 << SCALE_FREQ_SHFT; |
Taniya Das | 0e03aa2 | 2019-08-07 11:28:28 +0530 | [diff] [blame] | 107 | |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 108 | gpll0_cfg.reg_user_ctl = &gcc->gpll0.user_ctl; |
| 109 | gpll0_cfg.user_ctl_val = (1 << PLL_POST_DIV_EVEN_SHFT | |
| 110 | 1 << PLL_PLLOUT_EVEN_SHFT | |
| 111 | 1 << PLL_PLLOUT_MAIN_SHFT | |
| 112 | 1 << PLL_PLLOUT_ODD_SHFT); |
Taniya Das | 0e03aa2 | 2019-08-07 11:28:28 +0530 | [diff] [blame] | 113 | |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 114 | return clock_configure_enable_gpll(&gpll0_cfg, false, 0); |
Taniya Das | 0e03aa2 | 2019-08-07 11:28:28 +0530 | [diff] [blame] | 115 | } |
| 116 | |
| 117 | void clock_configure_qspi(uint32_t hz) |
| 118 | { |
| 119 | clock_configure(&gcc->qspi_core, |
| 120 | qspi_core_cfg, hz, |
| 121 | ARRAY_SIZE(qspi_core_cfg)); |
| 122 | clock_enable(&gcc->qspi_cnoc_ahb_cbcr); |
Taniya Das | dc92cea | 2019-07-08 12:00:51 +0530 | [diff] [blame] | 123 | clock_enable(&gcc->qspi_core_cbcr); |
Taniya Das | 0e03aa2 | 2019-08-07 11:28:28 +0530 | [diff] [blame] | 124 | } |
| 125 | |
Taniya Das | 310edec | 2021-06-23 08:53:39 +0530 | [diff] [blame] | 126 | void clock_configure_dfsr(int qup) |
Taniya Das | 0e03aa2 | 2019-08-07 11:28:28 +0530 | [diff] [blame] | 127 | { |
Taniya Das | 310edec | 2021-06-23 08:53:39 +0530 | [diff] [blame] | 128 | clock_configure_dfsr_table(qup, qupv3_wrap_cfg, |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 129 | ARRAY_SIZE(qupv3_wrap_cfg)); |
Taniya Das | 0e03aa2 | 2019-08-07 11:28:28 +0530 | [diff] [blame] | 130 | } |
| 131 | |
| 132 | void clock_enable_qup(int qup) |
| 133 | { |
| 134 | int s = qup % QUP_WRAP1_S0; |
| 135 | int clk_en_off = qup < QUP_WRAP1_S0 ? |
| 136 | QUPV3_WRAP0_CLK_ENA_S(s) : QUPV3_WRAP1_CLK_ENA_S(s); |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 137 | struct qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? |
Taniya Das | 0e03aa2 | 2019-08-07 11:28:28 +0530 | [diff] [blame] | 138 | &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; |
| 139 | |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 140 | clock_enable_vote(&qup_clk->cbcr, &gcc->apcs_clk_br_en1, |
| 141 | clk_en_off); |
Taniya Das | 310edec | 2021-06-23 08:53:39 +0530 | [diff] [blame] | 142 | } |
| 143 | |
| 144 | static enum cb_err pll_init_and_set(struct sc7180_apss_clock *apss, u32 l_val) |
| 145 | { |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 146 | struct alpha_pll_reg_val_config pll_cfg = {0}; |
Taniya Das | 310edec | 2021-06-23 08:53:39 +0530 | [diff] [blame] | 147 | int ret; |
Taniya Das | 8ad0c86 | 2020-02-28 17:05:49 +0530 | [diff] [blame] | 148 | u32 gfmux_val; |
| 149 | |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 150 | pll_cfg.reg_config_ctl = &apss->pll.config_ctl_lo; |
| 151 | pll_cfg.reg_config_ctl_hi = &apss->pll.config_ctl_hi; |
| 152 | pll_cfg.reg_config_ctl_hi1 = &apss->pll.config_ctl_u1; |
Taniya Das | 8ad0c86 | 2020-02-28 17:05:49 +0530 | [diff] [blame] | 153 | |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 154 | pll_cfg.config_ctl_val = (0x2 << CTUNE_SHFT | 0x2 << K_I_SHFT | |
| 155 | 0x5 << K_P_SHFT | 0x2 << PFA_MSB_SHFT | |
| 156 | 0x2 << REF_CONT_SHFT); |
| 157 | pll_cfg.config_ctl_hi_val = (0x2 << CUR_ADJ_SHFT | BIT(DMET_SHFT) | |
| 158 | 0xF << RES_SHFT); |
Taniya Das | 8ad0c86 | 2020-02-28 17:05:49 +0530 | [diff] [blame] | 159 | |
| 160 | write32(&apss->pll.config_ctl_u1, 0x0); |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 161 | pll_cfg.reg_l = &apss->pll.l; |
| 162 | pll_cfg.l_val = l_val; |
Taniya Das | 8ad0c86 | 2020-02-28 17:05:49 +0530 | [diff] [blame] | 163 | |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 164 | ret = clock_configure_enable_gpll(&pll_cfg, false, 0); |
Taniya Das | e3cf008 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 165 | if (ret != CB_SUCCESS) |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 166 | return CB_ERR; |
| 167 | |
| 168 | pll_cfg.reg_mode = &apss->pll.mode; |
| 169 | ret = agera_pll_enable(&pll_cfg); |
Taniya Das | e3cf008 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 170 | if (ret != CB_SUCCESS) |
Taniya Das | 310edec | 2021-06-23 08:53:39 +0530 | [diff] [blame] | 171 | return CB_ERR; |
Taniya Das | 8ad0c86 | 2020-02-28 17:05:49 +0530 | [diff] [blame] | 172 | |
| 173 | gfmux_val = read32(&apss->cfg_gfmux) & ~GFMUX_SRC_SEL_BMSK; |
| 174 | gfmux_val |= APCS_SRC_EARLY; |
| 175 | write32(&apss->cfg_gfmux, gfmux_val); |
| 176 | |
Taniya Das | 310edec | 2021-06-23 08:53:39 +0530 | [diff] [blame] | 177 | return CB_SUCCESS; |
Taniya Das | 8ad0c86 | 2020-02-28 17:05:49 +0530 | [diff] [blame] | 178 | } |
| 179 | |
| 180 | static void speed_up_boot_cpu(void) |
| 181 | { |
| 182 | /* 1516.8 MHz */ |
| 183 | if (!pll_init_and_set(apss_silver, L_VAL_1516P8MHz)) |
| 184 | printk(BIOS_DEBUG, "Silver Frequency bumped to 1.5168(GHz)\n"); |
| 185 | |
| 186 | /* 1209.6 MHz */ |
| 187 | if (!pll_init_and_set(apss_l3, L_VAL_1209P6MHz)) |
| 188 | printk(BIOS_DEBUG, "L3 Frequency bumped to 1.2096(GHz)\n"); |
| 189 | } |
| 190 | |
Taniya Das | 310edec | 2021-06-23 08:53:39 +0530 | [diff] [blame] | 191 | enum cb_err mdss_clock_configure(enum mdss_clock clk_type, uint32_t source, |
| 192 | uint32_t divider, uint32_t m, |
Taniya Das | dc92cea | 2019-07-08 12:00:51 +0530 | [diff] [blame] | 193 | uint32_t n, uint32_t d_2) |
| 194 | { |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 195 | struct clock_freq_config mdss_clk_cfg; |
Taniya Das | dc92cea | 2019-07-08 12:00:51 +0530 | [diff] [blame] | 196 | |
| 197 | if (clk_type >= MDSS_CLK_COUNT) |
Taniya Das | 310edec | 2021-06-23 08:53:39 +0530 | [diff] [blame] | 198 | return CB_ERR; |
Taniya Das | dc92cea | 2019-07-08 12:00:51 +0530 | [diff] [blame] | 199 | |
| 200 | /* Initialize it with received arguments */ |
| 201 | mdss_clk_cfg.hz = 0; |
| 202 | mdss_clk_cfg.src = source; |
| 203 | |
| 204 | /* |
Taniya Das | 310edec | 2021-06-23 08:53:39 +0530 | [diff] [blame] | 205 | * Update half_divider passed from display, this is to accommodate |
| 206 | * the transition to common clock driver. |
| 207 | * |
Taniya Das | dc92cea | 2019-07-08 12:00:51 +0530 | [diff] [blame] | 208 | * client is expected to provide 2n divider value, |
| 209 | * as the divider value in register is in form "2n-1" |
| 210 | */ |
Taniya Das | 310edec | 2021-06-23 08:53:39 +0530 | [diff] [blame] | 211 | mdss_clk_cfg.div = divider ? ((divider * 2) - 1) : 0; |
Taniya Das | dc92cea | 2019-07-08 12:00:51 +0530 | [diff] [blame] | 212 | mdss_clk_cfg.m = m; |
| 213 | mdss_clk_cfg.n = n; |
| 214 | mdss_clk_cfg.d_2 = d_2; |
| 215 | |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 216 | return clock_configure((struct clock_rcg *)mdss_clock[clk_type], |
Shelley Chen | 420ba8b | 2022-03-31 18:07:59 -0700 | [diff] [blame] | 217 | &mdss_clk_cfg, 0, 1); |
Taniya Das | dc92cea | 2019-07-08 12:00:51 +0530 | [diff] [blame] | 218 | } |
| 219 | |
| 220 | int mdss_clock_enable(enum mdss_clock clk_type) |
| 221 | { |
| 222 | if (clk_type >= MDSS_CLK_COUNT) |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 223 | return CB_ERR; |
Taniya Das | dc92cea | 2019-07-08 12:00:51 +0530 | [diff] [blame] | 224 | |
Taniya Das | e3cf008 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 225 | /* Enable clock */ |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 226 | return clock_enable(mdss_cbcr[clk_type]); |
Taniya Das | dc92cea | 2019-07-08 12:00:51 +0530 | [diff] [blame] | 227 | } |
| 228 | |
Taniya Das | 0e03aa2 | 2019-08-07 11:28:28 +0530 | [diff] [blame] | 229 | void clock_init(void) |
| 230 | { |
| 231 | clock_configure_gpll0(); |
| 232 | |
Taniya Das | dc92cea | 2019-07-08 12:00:51 +0530 | [diff] [blame] | 233 | clock_enable_vote(&gcc->qup_wrap0_core_2x_cbcr, |
Taniya Das | 0e03aa2 | 2019-08-07 11:28:28 +0530 | [diff] [blame] | 234 | &gcc->apcs_clk_br_en1, |
| 235 | QUPV3_WRAP0_CORE_2X_CLK_ENA); |
| 236 | clock_enable_vote(&gcc->qup_wrap0_core_cbcr, |
| 237 | &gcc->apcs_clk_br_en1, |
| 238 | QUPV3_WRAP0_CORE_CLK_ENA); |
| 239 | clock_enable_vote(&gcc->qup_wrap0_m_ahb_cbcr, |
| 240 | &gcc->apcs_clk_br_en1, |
| 241 | QUPV3_WRAP_0_M_AHB_CLK_ENA); |
| 242 | clock_enable_vote(&gcc->qup_wrap0_s_ahb_cbcr, |
| 243 | &gcc->apcs_clk_br_en1, |
| 244 | QUPV3_WRAP_0_S_AHB_CLK_ENA); |
| 245 | |
| 246 | clock_enable_vote(&gcc->qup_wrap1_core_2x_cbcr, |
| 247 | &gcc->apcs_clk_br_en1, |
| 248 | QUPV3_WRAP1_CORE_2X_CLK_ENA); |
| 249 | clock_enable_vote(&gcc->qup_wrap1_core_cbcr, |
| 250 | &gcc->apcs_clk_br_en1, |
| 251 | QUPV3_WRAP1_CORE_CLK_ENA); |
| 252 | clock_enable_vote(&gcc->qup_wrap1_m_ahb_cbcr, |
| 253 | &gcc->apcs_clk_br_en1, |
| 254 | QUPV3_WRAP_1_M_AHB_CLK_ENA); |
| 255 | clock_enable_vote(&gcc->qup_wrap1_s_ahb_cbcr, |
| 256 | &gcc->apcs_clk_br_en1, |
| 257 | QUPV3_WRAP_1_S_AHB_CLK_ENA); |
Taniya Das | 8ad0c86 | 2020-02-28 17:05:49 +0530 | [diff] [blame] | 258 | speed_up_boot_cpu(); |
Taniya Das | 0e03aa2 | 2019-08-07 11:28:28 +0530 | [diff] [blame] | 259 | } |