Angel Pons | a2ee761 | 2020-04-04 18:51:15 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* NVIDIA Tegra SPI controller (T114 and later) */ |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 3 | |
| 4 | #include <arch/cache.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 5 | #include <device/mmio.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 6 | #include <assert.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 7 | #include <console/console.h> |
| 8 | #include <delay.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 9 | #include <spi-generic.h> |
| 10 | #include <spi_flash.h> |
| 11 | #include <soc/addressmap.h> |
| 12 | #include <soc/dma.h> |
| 13 | #include <soc/spi.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 14 | #include <symbols.h> |
Elyes HAOUAS | 27d02d8 | 2019-05-15 21:11:39 +0200 | [diff] [blame] | 15 | #include <types.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 16 | |
| 17 | #if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI |
| 18 | # define DEBUG_SPI(x,...) printk(BIOS_DEBUG, "TEGRA_SPI: " x) |
| 19 | #else |
| 20 | # define DEBUG_SPI(x,...) |
| 21 | #endif |
| 22 | |
| 23 | /* |
| 24 | * 64 packets in FIFO mode, BLOCK_SIZE packets in DMA mode. Packets can vary |
| 25 | * in size from 4 to 32 bits. To keep things simple we'll use 8-bit packets. |
| 26 | */ |
| 27 | #define SPI_PACKET_SIZE_BYTES 1 |
| 28 | #define SPI_MAX_TRANSFER_BYTES_FIFO (64 * SPI_PACKET_SIZE_BYTES) |
| 29 | #define SPI_MAX_TRANSFER_BYTES_DMA (65535 * SPI_PACKET_SIZE_BYTES) |
| 30 | |
| 31 | /* |
| 32 | * This is used to workaround an issue seen where it may take some time for |
| 33 | * packets to show up in the FIFO after they have been received and the |
| 34 | * BLOCK_COUNT has been incremented. |
| 35 | */ |
| 36 | #define SPI_FIFO_XFER_TIMEOUT_US 1000 |
| 37 | |
| 38 | /* COMMAND1 */ |
| 39 | #define SPI_CMD1_GO (1 << 31) |
| 40 | #define SPI_CMD1_M_S (1 << 30) |
| 41 | #define SPI_CMD1_MODE_MASK 0x3 |
| 42 | #define SPI_CMD1_MODE_SHIFT 28 |
| 43 | #define SPI_CMD1_CS_SEL_MASK 0x3 |
| 44 | #define SPI_CMD1_CS_SEL_SHIFT 26 |
| 45 | #define SPI_CMD1_CS_POL_INACTIVE3 (1 << 25) |
| 46 | #define SPI_CMD1_CS_POL_INACTIVE2 (1 << 24) |
| 47 | #define SPI_CMD1_CS_POL_INACTIVE1 (1 << 23) |
| 48 | #define SPI_CMD1_CS_POL_INACTIVE0 (1 << 22) |
| 49 | #define SPI_CMD1_CS_SW_HW (1 << 21) |
| 50 | #define SPI_CMD1_CS_SW_VAL (1 << 20) |
| 51 | #define SPI_CMD1_IDLE_SDA_MASK 0x3 |
| 52 | #define SPI_CMD1_IDLE_SDA_SHIFT 18 |
| 53 | #define SPI_CMD1_BIDIR (1 << 17) |
| 54 | #define SPI_CMD1_LSBI_FE (1 << 16) |
| 55 | #define SPI_CMD1_LSBY_FE (1 << 15) |
| 56 | #define SPI_CMD1_BOTH_EN_BIT (1 << 14) |
| 57 | #define SPI_CMD1_BOTH_EN_BYTE (1 << 13) |
| 58 | #define SPI_CMD1_RX_EN (1 << 12) |
| 59 | #define SPI_CMD1_TX_EN (1 << 11) |
| 60 | #define SPI_CMD1_PACKED (1 << 5) |
| 61 | #define SPI_CMD1_BIT_LEN_MASK 0x1f |
| 62 | #define SPI_CMD1_BIT_LEN_SHIFT 0 |
| 63 | |
| 64 | /* COMMAND2 */ |
| 65 | #define SPI_CMD2_TX_CLK_TAP_DELAY (1 << 6) |
| 66 | #define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6) |
| 67 | #define SPI_CMD2_RX_CLK_TAP_DELAY (1 << 0) |
| 68 | #define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0) |
| 69 | |
| 70 | /* SPI_TRANS_STATUS */ |
| 71 | #define SPI_STATUS_RDY (1 << 30) |
| 72 | #define SPI_STATUS_SLV_IDLE_COUNT_MASK 0xff |
| 73 | #define SPI_STATUS_SLV_IDLE_COUNT_SHIFT 16 |
| 74 | #define SPI_STATUS_BLOCK_COUNT 0xffff |
| 75 | #define SPI_STATUS_BLOCK_COUNT_SHIFT 0 |
| 76 | |
| 77 | /* SPI_FIFO_STATUS */ |
| 78 | #define SPI_FIFO_STATUS_CS_INACTIVE (1 << 31) |
| 79 | #define SPI_FIFO_STATUS_FRAME_END (1 << 30) |
| 80 | #define SPI_FIFO_STATUS_RX_FIFO_FULL_COUNT_MASK 0x7f |
| 81 | #define SPI_FIFO_STATUS_RX_FIFO_FULL_COUNT_SHIFT 23 |
| 82 | #define SPI_FIFO_STATUS_TX_FIFO_EMPTY_COUNT_MASK 0x7f |
| 83 | #define SPI_FIFO_STATUS_TX_FIFO_EMPTY_COUNT_SHIFT 16 |
| 84 | #define SPI_FIFO_STATUS_RX_FIFO_FLUSH (1 << 15) |
| 85 | #define SPI_FIFO_STATUS_TX_FIFO_FLUSH (1 << 14) |
| 86 | #define SPI_FIFO_STATUS_ERR (1 << 8) |
| 87 | #define SPI_FIFO_STATUS_TX_FIFO_OVF (1 << 7) |
| 88 | #define SPI_FIFO_STATUS_TX_FIFO_UNR (1 << 6) |
| 89 | #define SPI_FIFO_STATUS_RX_FIFO_OVF (1 << 5) |
| 90 | #define SPI_FIFO_STATUS_RX_FIFO_UNR (1 << 4) |
| 91 | #define SPI_FIFO_STATUS_TX_FIFO_FULL (1 << 3) |
| 92 | #define SPI_FIFO_STATUS_TX_FIFO_EMPTY (1 << 2) |
| 93 | #define SPI_FIFO_STATUS_RX_FIFO_FULL (1 << 1) |
| 94 | #define SPI_FIFO_STATUS_RX_FIFO_EMPTY (1 << 0) |
| 95 | |
| 96 | /* SPI_DMA_CTL */ |
| 97 | #define SPI_DMA_CTL_DMA (1 << 31) |
| 98 | #define SPI_DMA_CTL_CONT (1 << 30) |
| 99 | #define SPI_DMA_CTL_IE_RX (1 << 29) |
| 100 | #define SPI_DMA_CTL_IE_TX (1 << 28) |
| 101 | #define SPI_DMA_CTL_RX_TRIG_MASK 0x3 |
| 102 | #define SPI_DMA_CTL_RX_TRIG_SHIFT 19 |
| 103 | #define SPI_DMA_CTL_TX_TRIG_MASK 0x3 |
| 104 | #define SPI_DMA_CTL_TX_TRIG_SHIFT 15 |
| 105 | |
| 106 | /* SPI_DMA_BLK */ |
| 107 | #define SPI_DMA_CTL_BLOCK_SIZE_MASK 0xffff |
| 108 | #define SPI_DMA_CTL_BLOCK_SIZE_SHIFT 0 |
| 109 | |
| 110 | static struct tegra_spi_channel tegra_spi_channels[] = { |
| 111 | /* |
| 112 | * Note: Tegra pinmux must be setup for corresponding SPI channel in |
| 113 | * order for its registers to be accessible. If pinmux has not been |
| 114 | * set up, access to the channel's registers will simply hang. |
| 115 | * |
| 116 | * TODO(dhendrix): Clarify or remove this comment (is clock setup |
| 117 | * necessary first, or just pinmux, or both?) |
| 118 | */ |
| 119 | { |
| 120 | .slave = { .bus = 1, }, |
| 121 | .regs = (struct tegra_spi_regs *)TEGRA_SPI1_BASE, |
| 122 | .req_sel = APBDMA_SLAVE_SL2B1, |
| 123 | }, |
| 124 | { |
| 125 | .slave = { .bus = 2, }, |
| 126 | .regs = (struct tegra_spi_regs *)TEGRA_SPI2_BASE, |
| 127 | .req_sel = APBDMA_SLAVE_SL2B2, |
| 128 | }, |
| 129 | { |
| 130 | .slave = { .bus = 3, }, |
| 131 | .regs = (struct tegra_spi_regs *)TEGRA_SPI3_BASE, |
| 132 | .req_sel = APBDMA_SLAVE_SL2B3, |
| 133 | }, |
| 134 | { |
| 135 | .slave = { .bus = 4, }, |
| 136 | .regs = (struct tegra_spi_regs *)TEGRA_SPI4_BASE, |
| 137 | .req_sel = APBDMA_SLAVE_SL2B4, |
| 138 | }, |
| 139 | { |
| 140 | .slave = { .bus = 5, }, |
| 141 | .regs = (struct tegra_spi_regs *)TEGRA_SPI5_BASE, |
| 142 | .req_sel = APBDMA_SLAVE_SL2B5, |
| 143 | }, |
| 144 | { |
| 145 | .slave = { .bus = 6, }, |
| 146 | .regs = (struct tegra_spi_regs *)TEGRA_SPI6_BASE, |
| 147 | .req_sel = APBDMA_SLAVE_SL2B6, |
| 148 | }, |
| 149 | { |
| 150 | .slave = { .bus = 7, }, |
| 151 | .regs = (struct tegra_spi_regs *)TEGRA_QSPI_BASE, |
| 152 | .req_sel = APBDMA_SLAVE_QSPI, |
| 153 | }, |
| 154 | }; |
| 155 | |
| 156 | enum spi_direction { |
| 157 | SPI_SEND, |
| 158 | SPI_RECEIVE, |
| 159 | }; |
| 160 | |
| 161 | struct tegra_spi_channel *tegra_spi_init(unsigned int bus) |
| 162 | { |
| 163 | int i; |
| 164 | struct tegra_spi_channel *spi = NULL; |
| 165 | |
| 166 | for (i = 0; i < ARRAY_SIZE(tegra_spi_channels); i++) { |
| 167 | if (tegra_spi_channels[i].slave.bus == bus) { |
| 168 | spi = &tegra_spi_channels[i]; |
| 169 | break; |
| 170 | } |
| 171 | } |
| 172 | if (!spi) |
| 173 | return NULL; |
| 174 | |
| 175 | /* software drives chip-select, set value to high */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 176 | setbits32(&spi->regs->command1, |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 177 | SPI_CMD1_CS_SW_HW | SPI_CMD1_CS_SW_VAL); |
| 178 | |
| 179 | /* 8-bit transfers, unpacked mode, most significant bit first */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 180 | clrbits32(&spi->regs->command1, |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 181 | SPI_CMD1_BIT_LEN_MASK | SPI_CMD1_PACKED); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 182 | setbits32(&spi->regs->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 183 | |
| 184 | return spi; |
| 185 | } |
| 186 | |
| 187 | static struct tegra_spi_channel * const to_tegra_spi(int bus) { |
| 188 | return &tegra_spi_channels[bus - 1]; |
| 189 | } |
| 190 | |
Furquan Shaikh | 94f8699 | 2016-12-01 07:12:32 -0800 | [diff] [blame] | 191 | static int spi_ctrlr_claim_bus(const struct spi_slave *slave) |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 192 | { |
| 193 | struct tegra_spi_regs *regs = to_tegra_spi(slave->bus)->regs; |
| 194 | u32 val; |
| 195 | |
| 196 | tegra_spi_init(slave->bus); |
| 197 | |
| 198 | val = read32(®s->command1); |
| 199 | |
| 200 | /* select appropriate chip-select line */ |
| 201 | val &= ~(SPI_CMD1_CS_SEL_MASK << SPI_CMD1_CS_SEL_SHIFT); |
| 202 | val |= (slave->cs << SPI_CMD1_CS_SEL_SHIFT); |
| 203 | |
| 204 | /* drive chip-select with the inverse of the "inactive" value */ |
| 205 | if (val & (SPI_CMD1_CS_POL_INACTIVE0 << slave->cs)) |
| 206 | val &= ~SPI_CMD1_CS_SW_VAL; |
| 207 | else |
| 208 | val |= SPI_CMD1_CS_SW_VAL; |
| 209 | |
| 210 | write32(®s->command1, val); |
| 211 | return 0; |
| 212 | } |
| 213 | |
Furquan Shaikh | 94f8699 | 2016-12-01 07:12:32 -0800 | [diff] [blame] | 214 | static void spi_ctrlr_release_bus(const struct spi_slave *slave) |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 215 | { |
| 216 | struct tegra_spi_regs *regs = to_tegra_spi(slave->bus)->regs; |
| 217 | u32 val; |
| 218 | |
| 219 | val = read32(®s->command1); |
| 220 | |
| 221 | if (val & (SPI_CMD1_CS_POL_INACTIVE0 << slave->cs)) |
| 222 | val |= SPI_CMD1_CS_SW_VAL; |
| 223 | else |
| 224 | val &= ~SPI_CMD1_CS_SW_VAL; |
| 225 | |
| 226 | write32(®s->command1, val); |
| 227 | } |
| 228 | |
| 229 | static void dump_fifo_status(struct tegra_spi_channel *spi) |
| 230 | { |
| 231 | u32 status = read32(&spi->regs->fifo_status); |
| 232 | |
| 233 | printk(BIOS_INFO, "Raw FIFO status: 0x%08x\n", status); |
| 234 | if (status & SPI_FIFO_STATUS_TX_FIFO_OVF) |
| 235 | printk(BIOS_INFO, "\tTx overflow detected\n"); |
| 236 | if (status & SPI_FIFO_STATUS_TX_FIFO_UNR) |
| 237 | printk(BIOS_INFO, "\tTx underrun detected\n"); |
| 238 | if (status & SPI_FIFO_STATUS_RX_FIFO_OVF) |
| 239 | printk(BIOS_INFO, "\tRx overflow detected\n"); |
| 240 | if (status & SPI_FIFO_STATUS_RX_FIFO_UNR) |
| 241 | printk(BIOS_INFO, "\tRx underrun detected\n"); |
| 242 | |
| 243 | printk(BIOS_INFO, "TX_FIFO: 0x%08x, TX_DATA: 0x%08x\n", |
| 244 | read32(&spi->regs->tx_fifo), read32(&spi->regs->tx_data)); |
| 245 | printk(BIOS_INFO, "RX_FIFO: 0x%08x, RX_DATA: 0x%08x\n", |
| 246 | read32(&spi->regs->rx_fifo), read32(&spi->regs->rx_data)); |
| 247 | } |
| 248 | |
| 249 | static void clear_fifo_status(struct tegra_spi_channel *spi) |
| 250 | { |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 251 | clrbits32(&spi->regs->fifo_status, |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 252 | SPI_FIFO_STATUS_ERR | |
| 253 | SPI_FIFO_STATUS_TX_FIFO_OVF | |
| 254 | SPI_FIFO_STATUS_TX_FIFO_UNR | |
| 255 | SPI_FIFO_STATUS_RX_FIFO_OVF | |
| 256 | SPI_FIFO_STATUS_RX_FIFO_UNR); |
| 257 | } |
| 258 | |
| 259 | static void dump_spi_regs(struct tegra_spi_channel *spi) |
| 260 | { |
| 261 | printk(BIOS_INFO, "SPI regs:\n" |
| 262 | "\tdma_blk: 0x%08x\n" |
| 263 | "\tcommand1: 0x%08x\n" |
| 264 | "\tdma_ctl: 0x%08x\n" |
| 265 | "\ttrans_status: 0x%08x\n", |
| 266 | read32(&spi->regs->dma_blk), |
| 267 | read32(&spi->regs->command1), |
| 268 | read32(&spi->regs->dma_ctl), |
| 269 | read32(&spi->regs->trans_status)); |
| 270 | } |
| 271 | |
| 272 | static void dump_dma_regs(struct apb_dma_channel *dma) |
| 273 | { |
Tim Wawrzynczak | 680027e | 2019-08-07 20:54:01 -0600 | [diff] [blame] | 274 | if (dma) { |
| 275 | printk(BIOS_INFO, "DMA regs:\n" |
| 276 | "\tahb_ptr: 0x%08x\n" |
| 277 | "\tapb_ptr: 0x%08x\n" |
| 278 | "\tahb_seq: 0x%08x\n" |
| 279 | "\tapb_seq: 0x%08x\n" |
| 280 | "\tcsr: 0x%08x\n" |
| 281 | "\tcsre: 0x%08x\n" |
| 282 | "\twcount: 0x%08x\n" |
| 283 | "\tdma_byte_sta: 0x%08x\n" |
| 284 | "\tword_transfer: 0x%08x\n", |
| 285 | read32(&dma->regs->ahb_ptr), |
| 286 | read32(&dma->regs->apb_ptr), |
| 287 | read32(&dma->regs->ahb_seq), |
| 288 | read32(&dma->regs->apb_seq), |
| 289 | read32(&dma->regs->csr), |
| 290 | read32(&dma->regs->csre), |
| 291 | read32(&dma->regs->wcount), |
| 292 | read32(&dma->regs->dma_byte_sta), |
| 293 | read32(&dma->regs->word_transfer)); |
| 294 | } |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 295 | } |
| 296 | |
| 297 | static inline unsigned int spi_byte_count(struct tegra_spi_channel *spi) |
| 298 | { |
| 299 | /* FIXME: Make this take total packet size into account */ |
| 300 | return read32(&spi->regs->trans_status) & |
| 301 | (SPI_STATUS_BLOCK_COUNT << SPI_STATUS_BLOCK_COUNT_SHIFT); |
| 302 | } |
| 303 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 304 | static void tegra_spi_wait(struct tegra_spi_channel *spi) |
| 305 | { |
Furquan Shaikh | 7731cdd | 2015-07-13 10:14:16 -0700 | [diff] [blame] | 306 | uint32_t dma_blk_count = 1 + (read32(&spi->regs->dma_blk) & |
| 307 | (SPI_DMA_CTL_BLOCK_SIZE_MASK << |
| 308 | SPI_DMA_CTL_BLOCK_SIZE_SHIFT)); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 309 | |
Furquan Shaikh | 7731cdd | 2015-07-13 10:14:16 -0700 | [diff] [blame] | 310 | while ((read32(&spi->regs->trans_status) & SPI_STATUS_RDY) != |
| 311 | SPI_STATUS_RDY) |
| 312 | ; |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 313 | |
Furquan Shaikh | 7731cdd | 2015-07-13 10:14:16 -0700 | [diff] [blame] | 314 | /* |
| 315 | * If RDY bit is set, we should never encounter the condition that |
| 316 | * blocks processed is not equal to the number programmed in dma_blk |
| 317 | * register. |
| 318 | */ |
| 319 | ASSERT(spi_byte_count(spi) == dma_blk_count); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 320 | } |
| 321 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 322 | static int fifo_error(struct tegra_spi_channel *spi) |
| 323 | { |
| 324 | return read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR ? 1 : 0; |
| 325 | } |
| 326 | |
Furquan Shaikh | 7731cdd | 2015-07-13 10:14:16 -0700 | [diff] [blame] | 327 | static void flush_fifos(struct tegra_spi_channel *spi) |
| 328 | { |
| 329 | const uint32_t flush_mask = SPI_FIFO_STATUS_TX_FIFO_FLUSH | |
| 330 | SPI_FIFO_STATUS_RX_FIFO_FLUSH; |
| 331 | |
| 332 | uint32_t fifo_status = read32(&spi->regs->fifo_status); |
| 333 | fifo_status |= flush_mask; |
| 334 | write32(&spi->regs->fifo_status, flush_mask); |
| 335 | |
| 336 | while (read32(&spi->regs->fifo_status) & flush_mask) |
| 337 | ; |
| 338 | } |
| 339 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 340 | static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi, |
| 341 | unsigned int bytes, enum spi_direction dir) |
| 342 | { |
| 343 | u8 *p = spi->out_buf; |
| 344 | unsigned int todo = MIN(bytes, SPI_MAX_TRANSFER_BYTES_FIFO); |
Furquan Shaikh | 7731cdd | 2015-07-13 10:14:16 -0700 | [diff] [blame] | 345 | u32 enable_mask; |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 346 | |
Furquan Shaikh | 7731cdd | 2015-07-13 10:14:16 -0700 | [diff] [blame] | 347 | flush_fifos(spi); |
| 348 | |
| 349 | if (dir == SPI_SEND) |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 350 | enable_mask = SPI_CMD1_TX_EN; |
Furquan Shaikh | 7731cdd | 2015-07-13 10:14:16 -0700 | [diff] [blame] | 351 | else |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 352 | enable_mask = SPI_CMD1_RX_EN; |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 353 | |
| 354 | /* |
| 355 | * BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and |
| 356 | * PIO transfers. And, it should be programmed before RX_EN or |
| 357 | * TX_EN is set. |
| 358 | */ |
| 359 | write32(&spi->regs->dma_blk, todo - 1); |
| 360 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 361 | setbits32(&spi->regs->command1, enable_mask); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 362 | |
| 363 | if (dir == SPI_SEND) { |
| 364 | unsigned int to_fifo = bytes; |
| 365 | while (to_fifo) { |
| 366 | write32(&spi->regs->tx_fifo, *p); |
| 367 | p++; |
| 368 | to_fifo--; |
| 369 | } |
| 370 | } |
| 371 | |
| 372 | return todo; |
| 373 | } |
| 374 | |
| 375 | static void tegra_spi_pio_start(struct tegra_spi_channel *spi) |
| 376 | { |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 377 | setbits32(&spi->regs->trans_status, SPI_STATUS_RDY); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 378 | /* |
| 379 | * Need to stabilize other reg bit before GO bit set. |
| 380 | * |
| 381 | * From IAS: |
| 382 | * For successful operation at various freq combinations, min of 4-5 |
| 383 | * spi_clk cycle delay might be required before enabling PIO or DMA bit. |
| 384 | * This is needed to overcome the MCP between core and pad_macro. |
| 385 | * The worst case delay calculation can be done considering slowest |
| 386 | * qspi_clk as 1 MHz. based on that 1 us delay should be enough before |
| 387 | * enabling pio or dma. |
| 388 | */ |
| 389 | udelay(2); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 390 | setbits32(&spi->regs->command1, SPI_CMD1_GO); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 391 | /* Need to wait a few cycles before command1 register is read */ |
| 392 | udelay(1); |
| 393 | /* Make sure the write to command1 completes. */ |
| 394 | read32(&spi->regs->command1); |
| 395 | } |
| 396 | |
| 397 | static inline u32 rx_fifo_count(struct tegra_spi_channel *spi) |
| 398 | { |
| 399 | return (read32(&spi->regs->fifo_status) >> |
| 400 | SPI_FIFO_STATUS_RX_FIFO_FULL_COUNT_SHIFT) & |
| 401 | SPI_FIFO_STATUS_RX_FIFO_FULL_COUNT_MASK; |
| 402 | } |
| 403 | |
| 404 | static int tegra_spi_pio_finish(struct tegra_spi_channel *spi) |
| 405 | { |
| 406 | u8 *p = spi->in_buf; |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 407 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 408 | clrbits32(&spi->regs->command1, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 409 | |
Furquan Shaikh | 7731cdd | 2015-07-13 10:14:16 -0700 | [diff] [blame] | 410 | ASSERT(rx_fifo_count(spi) == spi_byte_count(spi)); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 411 | |
Furquan Shaikh | 7731cdd | 2015-07-13 10:14:16 -0700 | [diff] [blame] | 412 | if (p) { |
| 413 | while (!(read32(&spi->regs->fifo_status) & |
| 414 | SPI_FIFO_STATUS_RX_FIFO_EMPTY)) { |
| 415 | *p = read8(&spi->regs->rx_fifo); |
| 416 | p++; |
| 417 | } |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 418 | } |
| 419 | |
| 420 | if (fifo_error(spi)) { |
| 421 | printk(BIOS_ERR, "%s: ERROR:\n", __func__); |
| 422 | dump_spi_regs(spi); |
| 423 | dump_fifo_status(spi); |
| 424 | return -1; |
| 425 | } |
| 426 | |
| 427 | return 0; |
| 428 | } |
| 429 | |
| 430 | static void setup_dma_params(struct tegra_spi_channel *spi, |
| 431 | struct apb_dma_channel *dma) |
| 432 | { |
| 433 | /* APB bus width = 8-bits, address wrap for each word */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 434 | clrbits32(&dma->regs->apb_seq, |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 435 | APB_BUS_WIDTH_MASK << APB_BUS_WIDTH_SHIFT); |
| 436 | /* AHB 1 word burst, bus width = 32 bits (fixed in hardware), |
| 437 | * no address wrapping */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 438 | clrsetbits32(&dma->regs->ahb_seq, |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 439 | (AHB_BURST_MASK << AHB_BURST_SHIFT), |
| 440 | 4 << AHB_BURST_SHIFT); |
| 441 | |
| 442 | /* Set ONCE mode to transfer one "block" at a time (64KB) and enable |
| 443 | * flow control. */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 444 | clrbits32(&dma->regs->csr, |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 445 | APB_CSR_REQ_SEL_MASK << APB_CSR_REQ_SEL_SHIFT); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 446 | setbits32(&dma->regs->csr, APB_CSR_ONCE | APB_CSR_FLOW | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 447 | (spi->req_sel << APB_CSR_REQ_SEL_SHIFT)); |
| 448 | } |
| 449 | |
| 450 | static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, |
| 451 | unsigned int bytes, enum spi_direction dir) |
| 452 | { |
| 453 | unsigned int todo, wcount; |
| 454 | |
| 455 | /* |
| 456 | * For DMA we need to think of things in terms of word count. |
| 457 | * AHB width is fixed at 32-bits. To avoid overrunning |
| 458 | * the in/out buffers we must align down. (Note: lowest 2-bits |
| 459 | * in WCOUNT register are ignored, and WCOUNT seems to count |
| 460 | * words starting at n-1) |
| 461 | * |
| 462 | * Example: If "bytes" is 7 and we are transferring 1-byte at a time, |
| 463 | * WCOUNT should be 4. The remaining 3 bytes must be transferred |
| 464 | * using PIO. |
| 465 | */ |
| 466 | todo = MIN(bytes, SPI_MAX_TRANSFER_BYTES_DMA - TEGRA_DMA_ALIGN_BYTES); |
| 467 | todo = ALIGN_DOWN(todo, TEGRA_DMA_ALIGN_BYTES); |
| 468 | wcount = ALIGN_DOWN(todo - TEGRA_DMA_ALIGN_BYTES, TEGRA_DMA_ALIGN_BYTES); |
| 469 | |
Furquan Shaikh | 7731cdd | 2015-07-13 10:14:16 -0700 | [diff] [blame] | 470 | flush_fifos(spi); |
| 471 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 472 | if (dir == SPI_SEND) { |
| 473 | spi->dma_out = dma_claim(); |
| 474 | if (!spi->dma_out) |
| 475 | return -1; |
| 476 | |
| 477 | /* ensure bytes to send will be visible to DMA controller */ |
| 478 | dcache_clean_by_mva(spi->out_buf, bytes); |
| 479 | |
| 480 | write32(&spi->dma_out->regs->apb_ptr, |
| 481 | (uintptr_t) & spi->regs->tx_fifo); |
| 482 | write32(&spi->dma_out->regs->ahb_ptr, (uintptr_t)spi->out_buf); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 483 | setbits32(&spi->dma_out->regs->csr, APB_CSR_DIR); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 484 | setup_dma_params(spi, spi->dma_out); |
| 485 | write32(&spi->dma_out->regs->wcount, wcount); |
| 486 | } else { |
| 487 | spi->dma_in = dma_claim(); |
| 488 | if (!spi->dma_in) |
| 489 | return -1; |
| 490 | |
| 491 | /* avoid data collisions */ |
| 492 | dcache_clean_invalidate_by_mva(spi->in_buf, bytes); |
| 493 | |
| 494 | write32(&spi->dma_in->regs->apb_ptr, |
| 495 | (uintptr_t)&spi->regs->rx_fifo); |
| 496 | write32(&spi->dma_in->regs->ahb_ptr, (uintptr_t)spi->in_buf); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 497 | clrbits32(&spi->dma_in->regs->csr, APB_CSR_DIR); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 498 | setup_dma_params(spi, spi->dma_in); |
| 499 | write32(&spi->dma_in->regs->wcount, wcount); |
| 500 | } |
| 501 | |
| 502 | /* BLOCK_SIZE starts at n-1 */ |
| 503 | write32(&spi->regs->dma_blk, todo - 1); |
| 504 | return todo; |
| 505 | } |
| 506 | |
| 507 | static void tegra_spi_dma_start(struct tegra_spi_channel *spi) |
| 508 | { |
| 509 | /* |
| 510 | * The RDY bit in SPI_TRANS_STATUS needs to be cleared manually |
| 511 | * (set bit to clear) between each transaction. Otherwise the next |
| 512 | * transaction does not start. |
| 513 | */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 514 | setbits32(&spi->regs->trans_status, SPI_STATUS_RDY); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 515 | |
| 516 | struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE; |
| 517 | |
| 518 | /* |
| 519 | * The DMA triggers have units of packets. As each packet is currently |
| 520 | * 1 byte the triggers need to be set to 4 packets (0b01) to match |
| 521 | * the AHB 32-bit (4 byte) tranfser. Otherwise the FIFO errors can |
| 522 | * occur. |
| 523 | */ |
| 524 | if (spi->dma_out) { |
| 525 | /* Enable secure access for the channel. */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 526 | setbits32(&apb_dma->security_reg, |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 527 | SECURITY_EN_BIT(spi->dma_out->num)); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 528 | clrsetbits32(&spi->regs->dma_ctl, |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 529 | SPI_DMA_CTL_TX_TRIG_MASK << SPI_DMA_CTL_TX_TRIG_SHIFT, |
| 530 | 1 << SPI_DMA_CTL_TX_TRIG_SHIFT); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 531 | setbits32(&spi->regs->command1, SPI_CMD1_TX_EN); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 532 | } |
| 533 | if (spi->dma_in) { |
| 534 | /* Enable secure access for the channel. */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 535 | setbits32(&apb_dma->security_reg, |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 536 | SECURITY_EN_BIT(spi->dma_in->num)); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 537 | clrsetbits32(&spi->regs->dma_ctl, |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 538 | SPI_DMA_CTL_RX_TRIG_MASK << SPI_DMA_CTL_RX_TRIG_SHIFT, |
| 539 | 1 << SPI_DMA_CTL_RX_TRIG_SHIFT); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 540 | setbits32(&spi->regs->command1, SPI_CMD1_RX_EN); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 541 | } |
| 542 | |
| 543 | /* |
| 544 | * To avoid underrun conditions, enable APB DMA before SPI DMA for |
| 545 | * Tx and enable SPI DMA before APB DMA before Rx. |
| 546 | */ |
| 547 | if (spi->dma_out) |
| 548 | dma_start(spi->dma_out); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 549 | setbits32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 550 | if (spi->dma_in) |
| 551 | dma_start(spi->dma_in); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 552 | } |
| 553 | |
| 554 | static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) |
| 555 | { |
| 556 | int ret; |
| 557 | unsigned int todo; |
| 558 | |
| 559 | struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE; |
| 560 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 561 | if (spi->dma_in) { |
Tim Wawrzynczak | 680027e | 2019-08-07 20:54:01 -0600 | [diff] [blame] | 562 | todo = read32(&spi->dma_in->regs->wcount); |
| 563 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 564 | while ((read32(&spi->dma_in->regs->dma_byte_sta) < todo) || |
| 565 | dma_busy(spi->dma_in)) |
Furquan Shaikh | 7731cdd | 2015-07-13 10:14:16 -0700 | [diff] [blame] | 566 | ; |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 567 | dma_stop(spi->dma_in); |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 568 | clrbits32(&spi->regs->command1, SPI_CMD1_RX_EN); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 569 | /* Disable secure access for the channel. */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 570 | clrbits32(&apb_dma->security_reg, |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 571 | SECURITY_EN_BIT(spi->dma_in->num)); |
| 572 | dma_release(spi->dma_in); |
| 573 | } |
| 574 | |
| 575 | if (spi->dma_out) { |
Tim Wawrzynczak | 680027e | 2019-08-07 20:54:01 -0600 | [diff] [blame] | 576 | todo = read32(&spi->dma_out->regs->wcount); |
| 577 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 578 | while ((read32(&spi->dma_out->regs->dma_byte_sta) < todo) || |
| 579 | dma_busy(spi->dma_out)) |
Furquan Shaikh | 7731cdd | 2015-07-13 10:14:16 -0700 | [diff] [blame] | 580 | ; |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 581 | clrbits32(&spi->regs->command1, SPI_CMD1_TX_EN); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 582 | dma_stop(spi->dma_out); |
| 583 | /* Disable secure access for the channel. */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 584 | clrbits32(&apb_dma->security_reg, |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 585 | SECURITY_EN_BIT(spi->dma_out->num)); |
| 586 | dma_release(spi->dma_out); |
| 587 | } |
| 588 | |
| 589 | if (fifo_error(spi)) { |
| 590 | printk(BIOS_ERR, "%s: ERROR:\n", __func__); |
| 591 | dump_dma_regs(spi->dma_out); |
| 592 | dump_dma_regs(spi->dma_in); |
| 593 | dump_spi_regs(spi); |
| 594 | dump_fifo_status(spi); |
| 595 | ret = -1; |
| 596 | goto done; |
| 597 | } |
| 598 | |
| 599 | ret = 0; |
| 600 | done: |
| 601 | spi->dma_in = NULL; |
| 602 | spi->dma_out = NULL; |
| 603 | return ret; |
| 604 | } |
| 605 | |
| 606 | /* |
| 607 | * xfer_setup() prepares a transfer. It does sanity checking, alignment, and |
| 608 | * sets transfer mode used by this channel (if not set already). |
| 609 | * |
| 610 | * A few caveats to watch out for: |
| 611 | * - The number of bytes which can be transferred may be smaller than the |
| 612 | * number of bytes the caller specifies. The number of bytes ready for |
| 613 | * a transfer will be returned (unless an error occurs). |
| 614 | * |
| 615 | * - Only one mode can be used for both RX and TX. The transfer mode of the |
| 616 | * SPI channel (spi->xfer_mode) is checked each time this function is called. |
| 617 | * If conflicting modes are detected, spi->xfer_mode will be set to |
| 618 | * XFER_MODE_NONE and an error will be returned. |
| 619 | * |
| 620 | * Returns bytes ready for transfer if successful, <0 to indicate error. |
| 621 | */ |
| 622 | static int xfer_setup(struct tegra_spi_channel *spi, void *buf, |
| 623 | unsigned int bytes, enum spi_direction dir) |
| 624 | { |
| 625 | unsigned int line_size = dcache_line_bytes(); |
| 626 | unsigned int align; |
| 627 | int ret = -1; |
| 628 | |
| 629 | if (!bytes) |
| 630 | return 0; |
| 631 | |
| 632 | if (dir == SPI_SEND) |
| 633 | spi->out_buf = buf; |
| 634 | else if (dir == SPI_RECEIVE) |
| 635 | spi->in_buf = buf; |
| 636 | |
| 637 | /* |
| 638 | * Alignment consideratons: |
| 639 | * When we enable caching we'll need to clean/invalidate portions of |
| 640 | * memory. So we need to be careful about memory alignment. Also, DMA |
| 641 | * likes to operate on 4-bytes at a time on the AHB side. So for |
Elyes HAOUAS | b9d95c5 | 2021-01-16 14:55:30 +0100 | [diff] [blame] | 642 | * example, if we only want to receive 1 byte, 4 bytes will be |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 643 | * written in memory even if those extra 3 bytes are beyond the length |
| 644 | * we want. |
| 645 | * |
| 646 | * For now we'll use PIO to send/receive unaligned bytes. We may |
| 647 | * consider setting aside some space for a kind of bounce buffer to |
| 648 | * stay in DMA mode once we have a chance to benchmark the two |
| 649 | * approaches. |
| 650 | */ |
| 651 | |
| 652 | if (bytes < line_size) { |
| 653 | if (spi->xfer_mode == XFER_MODE_DMA) { |
| 654 | spi->xfer_mode = XFER_MODE_NONE; |
| 655 | ret = -1; |
| 656 | } else { |
| 657 | spi->xfer_mode = XFER_MODE_PIO; |
| 658 | ret = tegra_spi_pio_prepare(spi, bytes, dir); |
| 659 | } |
| 660 | goto done; |
| 661 | } |
| 662 | |
| 663 | /* transfer bytes before the aligned boundary */ |
| 664 | align = line_size - ((uintptr_t)buf % line_size); |
| 665 | if ((align != 0) && (align != line_size)) { |
| 666 | if (spi->xfer_mode == XFER_MODE_DMA) { |
| 667 | spi->xfer_mode = XFER_MODE_NONE; |
| 668 | ret = -1; |
| 669 | } else { |
| 670 | spi->xfer_mode = XFER_MODE_PIO; |
| 671 | ret = tegra_spi_pio_prepare(spi, align, dir); |
| 672 | } |
| 673 | goto done; |
| 674 | } |
| 675 | |
| 676 | /* do aligned DMA transfer */ |
| 677 | align = (((uintptr_t)buf + bytes) % line_size); |
| 678 | if (bytes - align > 0) { |
| 679 | unsigned int dma_bytes = bytes - align; |
| 680 | |
| 681 | if (spi->xfer_mode == XFER_MODE_PIO) { |
| 682 | spi->xfer_mode = XFER_MODE_NONE; |
| 683 | ret = -1; |
| 684 | } else { |
| 685 | spi->xfer_mode = XFER_MODE_DMA; |
| 686 | ret = tegra_spi_dma_prepare(spi, dma_bytes, dir); |
| 687 | } |
| 688 | |
| 689 | goto done; |
| 690 | } |
| 691 | |
| 692 | /* transfer any remaining unaligned bytes */ |
| 693 | if (align) { |
| 694 | if (spi->xfer_mode == XFER_MODE_DMA) { |
| 695 | spi->xfer_mode = XFER_MODE_NONE; |
| 696 | ret = -1; |
| 697 | } else { |
| 698 | spi->xfer_mode = XFER_MODE_PIO; |
| 699 | ret = tegra_spi_pio_prepare(spi, align, dir); |
| 700 | } |
| 701 | goto done; |
| 702 | } |
| 703 | |
| 704 | done: |
| 705 | return ret; |
| 706 | } |
| 707 | |
| 708 | static void xfer_start(struct tegra_spi_channel *spi) |
| 709 | { |
| 710 | if (spi->xfer_mode == XFER_MODE_DMA) |
| 711 | tegra_spi_dma_start(spi); |
| 712 | else |
| 713 | tegra_spi_pio_start(spi); |
| 714 | } |
| 715 | |
| 716 | static void xfer_wait(struct tegra_spi_channel *spi) |
| 717 | { |
| 718 | tegra_spi_wait(spi); |
| 719 | } |
| 720 | |
| 721 | static int xfer_finish(struct tegra_spi_channel *spi) |
| 722 | { |
| 723 | int ret; |
| 724 | |
| 725 | if (spi->xfer_mode == XFER_MODE_DMA) |
| 726 | ret = tegra_spi_dma_finish(spi); |
| 727 | else |
| 728 | ret = tegra_spi_pio_finish(spi); |
| 729 | |
| 730 | spi->xfer_mode = XFER_MODE_NONE; |
| 731 | return ret; |
| 732 | } |
| 733 | |
Furquan Shaikh | 94f8699 | 2016-12-01 07:12:32 -0800 | [diff] [blame] | 734 | static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, |
| 735 | size_t out_bytes, void *din, size_t in_bytes) |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 736 | { |
| 737 | struct tegra_spi_channel *spi = to_tegra_spi(slave->bus); |
| 738 | u8 *out_buf = (u8 *)dout; |
| 739 | u8 *in_buf = (u8 *)din; |
Furquan Shaikh | 0dba025 | 2016-11-30 04:34:22 -0800 | [diff] [blame] | 740 | size_t todo; |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 741 | int ret = 0; |
| 742 | |
| 743 | /* tegra bus numbers start at 1 */ |
| 744 | ASSERT(slave->bus >= 1 && slave->bus <= ARRAY_SIZE(tegra_spi_channels)); |
| 745 | |
| 746 | while (out_bytes || in_bytes) { |
| 747 | int x = 0; |
| 748 | |
| 749 | if (out_bytes == 0) |
| 750 | todo = in_bytes; |
| 751 | else if (in_bytes == 0) |
| 752 | todo = out_bytes; |
| 753 | else |
| 754 | todo = MIN(out_bytes, in_bytes); |
| 755 | |
| 756 | if (out_bytes) { |
| 757 | x = xfer_setup(spi, out_buf, todo, SPI_SEND); |
| 758 | if (x < 0) { |
| 759 | if (spi->xfer_mode == XFER_MODE_NONE) { |
| 760 | spi->xfer_mode = XFER_MODE_PIO; |
| 761 | continue; |
| 762 | } else { |
| 763 | ret = -1; |
| 764 | break; |
| 765 | } |
| 766 | } |
| 767 | } |
| 768 | if (in_bytes) { |
| 769 | x = xfer_setup(spi, in_buf, todo, SPI_RECEIVE); |
| 770 | if (x < 0) { |
| 771 | if (spi->xfer_mode == XFER_MODE_NONE) { |
| 772 | spi->xfer_mode = XFER_MODE_PIO; |
| 773 | continue; |
| 774 | } else { |
| 775 | ret = -1; |
| 776 | break; |
| 777 | } |
| 778 | } |
| 779 | } |
| 780 | |
| 781 | /* |
| 782 | * Note: Some devices (such as Chrome EC) are sensitive to |
| 783 | * delays, so be careful when adding debug prints not to |
| 784 | * cause timeouts between transfers. |
| 785 | */ |
| 786 | xfer_start(spi); |
| 787 | xfer_wait(spi); |
| 788 | if (xfer_finish(spi)) { |
| 789 | ret = -1; |
| 790 | break; |
| 791 | } |
| 792 | |
| 793 | /* Post-processing. */ |
| 794 | if (out_bytes) { |
| 795 | out_bytes -= x; |
| 796 | out_buf += x; |
| 797 | } |
| 798 | if (in_bytes) { |
| 799 | in_bytes -= x; |
| 800 | in_buf += x; |
| 801 | } |
| 802 | } |
| 803 | |
| 804 | if (ret < 0) { |
| 805 | printk(BIOS_ERR, "%s: Error detected\n", __func__); |
Furquan Shaikh | 0dba025 | 2016-11-30 04:34:22 -0800 | [diff] [blame] | 806 | printk(BIOS_ERR, "Transaction size: %zu, bytes remaining: " |
| 807 | "%zu out / %zu in\n", todo, out_bytes, in_bytes); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 808 | clear_fifo_status(spi); |
| 809 | } |
| 810 | return ret; |
| 811 | } |
| 812 | |
Furquan Shaikh | 94f8699 | 2016-12-01 07:12:32 -0800 | [diff] [blame] | 813 | static const struct spi_ctrlr spi_ctrlr = { |
| 814 | .claim_bus = spi_ctrlr_claim_bus, |
| 815 | .release_bus = spi_ctrlr_release_bus, |
| 816 | .xfer = spi_ctrlr_xfer, |
Furquan Shaikh | de705fa | 2017-04-19 19:27:28 -0700 | [diff] [blame] | 817 | .max_xfer_size = SPI_CTRLR_DEFAULT_MAX_XFER_SIZE, |
Furquan Shaikh | 94f8699 | 2016-12-01 07:12:32 -0800 | [diff] [blame] | 818 | }; |
| 819 | |
Furquan Shaikh | b46e9f6 | 2017-05-18 10:46:46 -0700 | [diff] [blame] | 820 | const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { |
| 821 | { |
| 822 | .ctrlr = &spi_ctrlr, |
| 823 | .bus_start = 1, |
| 824 | .bus_end = ARRAY_SIZE(tegra_spi_channels) |
| 825 | }, |
| 826 | }; |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 827 | |
Furquan Shaikh | b46e9f6 | 2017-05-18 10:46:46 -0700 | [diff] [blame] | 828 | const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); |