Roger Lu | a5f472b | 2020-07-10 15:29:31 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
Roger Lu | a5f472b | 2020-07-10 15:29:31 +0800 | [diff] [blame] | 4 | #include <console/console.h> |
| 5 | #include <delay.h> |
| 6 | #include <device/mmio.h> |
| 7 | #include <soc/mcu_common.h> |
| 8 | #include <soc/spm.h> |
Rex-BC Chen | 8037376 | 2021-06-01 11:22:32 +0800 | [diff] [blame] | 9 | #include <soc/spm_common.h> |
Roger Lu | a5f472b | 2020-07-10 15:29:31 +0800 | [diff] [blame] | 10 | #include <soc/symbols.h> |
Roger Lu | a5f472b | 2020-07-10 15:29:31 +0800 | [diff] [blame] | 11 | #include <timer.h> |
| 12 | |
| 13 | #define SPM_SYSTEM_BASE_OFFSET 0x40000000 |
Roger Lu | a5f472b | 2020-07-10 15:29:31 +0800 | [diff] [blame] | 14 | |
| 15 | static const struct pwr_ctrl spm_init_ctrl = { |
| 16 | /* Auto-gen Start */ |
| 17 | |
| 18 | .pcm_flags = SPM_FLAG_DISABLE_VCORE_DVS | SPM_FLAG_DISABLE_VCORE_DFS | |
| 19 | SPM_FLAG_RUN_COMMON_SCENARIO, |
| 20 | |
| 21 | /* SPM_SRC6_MASK */ |
| 22 | .reg_dpmaif_srcclkena_mask_b = 1, |
| 23 | .reg_dpmaif_infra_req_mask_b = 1, |
| 24 | .reg_dpmaif_apsrc_req_mask_b = 1, |
| 25 | .reg_dpmaif_vrf18_req_mask_b = 1, |
| 26 | .reg_dpmaif_ddr_en_mask_b = 1, |
| 27 | |
| 28 | /* SPM_SRC_REQ */ |
| 29 | .reg_spm_ddr_en_req = 1, |
| 30 | |
| 31 | /* SPM_SRC_MASK */ |
| 32 | .reg_md_srcclkena_0_mask_b = 1, |
| 33 | .reg_md_apsrc2infra_req_0_mask_b = 1, |
| 34 | .reg_md_apsrc_req_0_mask_b = 1, |
| 35 | .reg_md_vrf18_req_0_mask_b = 1, |
| 36 | .reg_md_ddr_en_0_mask_b = 1, |
| 37 | .reg_conn_srcclkena_mask_b = 1, |
| 38 | .reg_conn_infra_req_mask_b = 1, |
| 39 | .reg_conn_apsrc_req_mask_b = 1, |
| 40 | .reg_conn_vrf18_req_mask_b = 1, |
| 41 | .reg_conn_ddr_en_mask_b = 1, |
| 42 | .reg_srcclkeni0_srcclkena_mask_b = 1, |
| 43 | .reg_srcclkeni0_infra_req_mask_b = 1, |
| 44 | .reg_infrasys_ddr_en_mask_b = 1, |
| 45 | .reg_md32_srcclkena_mask_b = 1, |
| 46 | .reg_md32_infra_req_mask_b = 1, |
| 47 | .reg_md32_apsrc_req_mask_b = 1, |
| 48 | .reg_md32_vrf18_req_mask_b = 1, |
| 49 | .reg_md32_ddr_en_mask_b = 1, |
| 50 | |
| 51 | /* SPM_SRC2_MASK */ |
| 52 | .reg_scp_srcclkena_mask_b = 1, |
| 53 | .reg_scp_infra_req_mask_b = 1, |
| 54 | .reg_scp_apsrc_req_mask_b = 1, |
| 55 | .reg_scp_vrf18_req_mask_b = 1, |
| 56 | .reg_scp_ddr_en_mask_b = 1, |
| 57 | .reg_audio_dsp_srcclkena_mask_b = 1, |
| 58 | .reg_audio_dsp_infra_req_mask_b = 1, |
| 59 | .reg_audio_dsp_apsrc_req_mask_b = 1, |
| 60 | .reg_audio_dsp_vrf18_req_mask_b = 1, |
| 61 | .reg_audio_dsp_ddr_en_mask_b = 1, |
| 62 | .reg_ufs_srcclkena_mask_b = 1, |
| 63 | .reg_ufs_infra_req_mask_b = 1, |
| 64 | .reg_ufs_apsrc_req_mask_b = 1, |
| 65 | .reg_ufs_vrf18_req_mask_b = 1, |
| 66 | .reg_ufs_ddr_en_mask_b = 1, |
| 67 | .reg_disp0_apsrc_req_mask_b = 1, |
| 68 | .reg_disp0_ddr_en_mask_b = 1, |
| 69 | .reg_disp1_apsrc_req_mask_b = 1, |
| 70 | .reg_disp1_ddr_en_mask_b = 1, |
| 71 | .reg_gce_infra_req_mask_b = 1, |
| 72 | .reg_gce_apsrc_req_mask_b = 1, |
| 73 | .reg_gce_vrf18_req_mask_b = 1, |
| 74 | .reg_gce_ddr_en_mask_b = 1, |
| 75 | .reg_apu_srcclkena_mask_b = 1, |
| 76 | .reg_apu_infra_req_mask_b = 1, |
| 77 | .reg_apu_apsrc_req_mask_b = 1, |
| 78 | .reg_apu_vrf18_req_mask_b = 1, |
| 79 | .reg_apu_ddr_en_mask_b = 1, |
| 80 | |
| 81 | /* SPM_SRC3_MASK */ |
| 82 | .reg_dvfsrc_event_trigger_mask_b = 1, |
| 83 | .reg_csyspwrreq_mask = 1, |
| 84 | .reg_mcupm_srcclkena_mask_b = 1, |
| 85 | .reg_mcupm_infra_req_mask_b = 1, |
| 86 | .reg_mcupm_apsrc_req_mask_b = 1, |
| 87 | .reg_mcupm_vrf18_req_mask_b = 1, |
| 88 | .reg_mcupm_ddr_en_mask_b = 1, |
| 89 | .reg_msdc0_srcclkena_mask_b = 1, |
| 90 | .reg_msdc0_infra_req_mask_b = 1, |
| 91 | .reg_msdc0_apsrc_req_mask_b = 1, |
| 92 | .reg_msdc0_vrf18_req_mask_b = 1, |
| 93 | .reg_msdc0_ddr_en_mask_b = 1, |
| 94 | .reg_msdc1_srcclkena_mask_b = 1, |
| 95 | .reg_msdc1_infra_req_mask_b = 1, |
| 96 | .reg_msdc1_apsrc_req_mask_b = 1, |
| 97 | .reg_msdc1_vrf18_req_mask_b = 1, |
| 98 | .reg_msdc1_ddr_en_mask_b = 1, |
| 99 | |
| 100 | /* SPM_SRC4_MASK */ |
| 101 | .ccif_event_mask_b = 0xFFF, |
| 102 | .reg_dramc0_md32_infra_req_mask_b = 1, |
| 103 | .reg_dramc1_md32_infra_req_mask_b = 1, |
| 104 | .reg_dramc0_md32_wakeup_mask = 1, |
| 105 | .reg_dramc1_md32_wakeup_mask = 1, |
| 106 | |
| 107 | /* SPM_SRC5_MASK */ |
| 108 | .reg_mcusys_merge_apsrc_req_mask_b = 0x11, |
| 109 | .reg_mcusys_merge_ddr_en_mask_b = 0x11, |
| 110 | .reg_msdc2_srcclkena_mask_b = 1, |
| 111 | .reg_msdc2_infra_req_mask_b = 1, |
| 112 | .reg_msdc2_apsrc_req_mask_b = 1, |
| 113 | .reg_msdc2_vrf18_req_mask_b = 1, |
| 114 | .reg_msdc2_ddr_en_mask_b = 1, |
| 115 | .reg_pcie_srcclkena_mask_b = 1, |
| 116 | .reg_pcie_infra_req_mask_b = 1, |
| 117 | .reg_pcie_apsrc_req_mask_b = 1, |
| 118 | .reg_pcie_vrf18_req_mask_b = 1, |
| 119 | .reg_pcie_ddr_en_mask_b = 1, |
| 120 | |
| 121 | /* SPM_WAKEUP_EVENT_MASK */ |
| 122 | .reg_wakeup_event_mask = 0xEFFFFFFF, |
| 123 | |
| 124 | /* SPM_WAKEUP_EVENT_EXT_MASK */ |
| 125 | .reg_ext_wakeup_event_mask = 0xFFFFFFFF, |
| 126 | |
| 127 | /* Auto-gen End */ |
| 128 | }; |
| 129 | |
| 130 | static void spm_set_power_control(const struct pwr_ctrl *pwrctrl) |
| 131 | { |
| 132 | /* Auto-gen Start */ |
| 133 | |
| 134 | /* SPM_AP_STANDBY_CON */ |
| 135 | write32(&mtk_spm->spm_ap_standby_con, |
| 136 | ((pwrctrl->reg_wfi_op & 0x1) << 0) | |
| 137 | ((pwrctrl->reg_wfi_type & 0x1) << 1) | |
| 138 | ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) | |
| 139 | ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) | |
| 140 | ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) | |
| 141 | ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) | |
| 142 | ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) | |
| 143 | ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29)); |
| 144 | |
| 145 | /* SPM_SRC6_MASK */ |
| 146 | write32(&mtk_spm->spm_src6_mask, |
| 147 | ((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 0) | |
| 148 | ((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 1) | |
| 149 | ((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 2) | |
| 150 | ((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 3) | |
| 151 | ((pwrctrl->reg_dpmaif_ddr_en_mask_b & 0x1) << 4)); |
| 152 | |
| 153 | /* SPM_SRC_REQ */ |
| 154 | write32(&mtk_spm->spm_src_req, |
| 155 | ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) | |
| 156 | ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) | |
| 157 | ((pwrctrl->reg_spm_infra_req & 0x1) << 3) | |
| 158 | ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) | |
| 159 | ((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) | |
| 160 | ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) | |
| 161 | ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) | |
| 162 | ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) | |
| 163 | ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) | |
| 164 | ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12)); |
| 165 | |
| 166 | /* SPM_SRC_MASK */ |
| 167 | write32(&mtk_spm->spm_src_mask, |
| 168 | ((pwrctrl->reg_md_srcclkena_0_mask_b & 0x1) << 0) | |
| 169 | ((pwrctrl->reg_md_srcclkena2infra_req_0_mask_b & 0x1) << 1) | |
| 170 | ((pwrctrl->reg_md_apsrc2infra_req_0_mask_b & 0x1) << 2) | |
| 171 | ((pwrctrl->reg_md_apsrc_req_0_mask_b & 0x1) << 3) | |
| 172 | ((pwrctrl->reg_md_vrf18_req_0_mask_b & 0x1) << 4) | |
| 173 | ((pwrctrl->reg_md_ddr_en_0_mask_b & 0x1) << 5) | |
| 174 | ((pwrctrl->reg_md_srcclkena_1_mask_b & 0x1) << 6) | |
| 175 | ((pwrctrl->reg_md_srcclkena2infra_req_1_mask_b & 0x1) << 7) | |
| 176 | ((pwrctrl->reg_md_apsrc2infra_req_1_mask_b & 0x1) << 8) | |
| 177 | ((pwrctrl->reg_md_apsrc_req_1_mask_b & 0x1) << 9) | |
| 178 | ((pwrctrl->reg_md_vrf18_req_1_mask_b & 0x1) << 10) | |
| 179 | ((pwrctrl->reg_md_ddr_en_1_mask_b & 0x1) << 11) | |
| 180 | ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 12) | |
| 181 | ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 13) | |
| 182 | ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 14) | |
| 183 | ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 15) | |
| 184 | ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 16) | |
| 185 | ((pwrctrl->reg_conn_ddr_en_mask_b & 0x1) << 17) | |
| 186 | ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 18) | |
| 187 | ((pwrctrl->reg_srcclkeni0_srcclkena_mask_b & 0x1) << 19) | |
| 188 | ((pwrctrl->reg_srcclkeni0_infra_req_mask_b & 0x1) << 20) | |
| 189 | ((pwrctrl->reg_srcclkeni1_srcclkena_mask_b & 0x1) << 21) | |
| 190 | ((pwrctrl->reg_srcclkeni1_infra_req_mask_b & 0x1) << 22) | |
| 191 | ((pwrctrl->reg_srcclkeni2_srcclkena_mask_b & 0x1) << 23) | |
| 192 | ((pwrctrl->reg_srcclkeni2_infra_req_mask_b & 0x1) << 24) | |
| 193 | ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) | |
| 194 | ((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 26) | |
| 195 | ((pwrctrl->reg_md32_srcclkena_mask_b & 0x1) << 27) | |
| 196 | ((pwrctrl->reg_md32_infra_req_mask_b & 0x1) << 28) | |
| 197 | ((pwrctrl->reg_md32_apsrc_req_mask_b & 0x1) << 29) | |
| 198 | ((pwrctrl->reg_md32_vrf18_req_mask_b & 0x1) << 30) | |
| 199 | ((pwrctrl->reg_md32_ddr_en_mask_b & 0x1) << 31)); |
| 200 | |
| 201 | /* SPM_SRC2_MASK */ |
| 202 | write32(&mtk_spm->spm_src2_mask, |
| 203 | ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) | |
| 204 | ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) | |
| 205 | ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) | |
| 206 | ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) | |
| 207 | ((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 4) | |
| 208 | ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) | |
| 209 | ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) | |
| 210 | ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) | |
| 211 | ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) | |
| 212 | ((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 9) | |
| 213 | ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) | |
| 214 | ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) | |
| 215 | ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) | |
| 216 | ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) | |
| 217 | ((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 14) | |
| 218 | ((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) | |
| 219 | ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 16) | |
| 220 | ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) | |
| 221 | ((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 18) | |
| 222 | ((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) | |
| 223 | ((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) | |
| 224 | ((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) | |
| 225 | ((pwrctrl->reg_gce_ddr_en_mask_b & 0x1) << 22) | |
| 226 | ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) | |
| 227 | ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) | |
| 228 | ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) | |
| 229 | ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) | |
| 230 | ((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 27) | |
| 231 | ((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) | |
| 232 | ((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) | |
| 233 | ((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) | |
| 234 | ((pwrctrl->reg_cg_check_ddr_en_mask_b & 0x1) << 31)); |
| 235 | |
| 236 | /* SPM_SRC3_MASK */ |
| 237 | write32(&mtk_spm->spm_src3_mask, |
| 238 | ((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) | |
| 239 | ((pwrctrl->reg_sw2spm_int0_mask_b & 0x1) << 1) | |
| 240 | ((pwrctrl->reg_sw2spm_int1_mask_b & 0x1) << 2) | |
| 241 | ((pwrctrl->reg_sw2spm_int2_mask_b & 0x1) << 3) | |
| 242 | ((pwrctrl->reg_sw2spm_int3_mask_b & 0x1) << 4) | |
| 243 | ((pwrctrl->reg_sc_adsp2spm_wakeup_mask_b & 0x1) << 5) | |
| 244 | ((pwrctrl->reg_sc_sspm2spm_wakeup_mask_b & 0xf) << 6) | |
| 245 | ((pwrctrl->reg_sc_scp2spm_wakeup_mask_b & 0x1) << 10) | |
| 246 | ((pwrctrl->reg_csyspwrreq_mask & 0x1) << 11) | |
| 247 | ((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 12) | |
| 248 | ((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 13) | |
| 249 | ((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 14) | |
| 250 | ((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 15) | |
| 251 | ((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 16) | |
| 252 | ((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) | |
| 253 | ((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) | |
| 254 | ((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) | |
| 255 | ((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) | |
| 256 | ((pwrctrl->reg_mcupm_ddr_en_mask_b & 0x1) << 21) | |
| 257 | ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) | |
| 258 | ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) | |
| 259 | ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) | |
| 260 | ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) | |
| 261 | ((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 26) | |
| 262 | ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) | |
| 263 | ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) | |
| 264 | ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) | |
| 265 | ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) | |
| 266 | ((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 31)); |
| 267 | |
| 268 | /* SPM_SRC4_MASK */ |
| 269 | write32(&mtk_spm->spm_src4_mask, |
| 270 | ((pwrctrl->ccif_event_mask_b & 0xffff) << 0) | |
| 271 | ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) | |
| 272 | ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) | |
| 273 | ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) | |
| 274 | ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) | |
| 275 | ((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 20) | |
| 276 | ((pwrctrl->reg_dramc0_md32_infra_req_mask_b & 0x1) << 21) | |
| 277 | ((pwrctrl->reg_dramc0_md32_vrf18_req_mask_b & 0x1) << 22) | |
| 278 | ((pwrctrl->reg_dramc1_md32_infra_req_mask_b & 0x1) << 23) | |
| 279 | ((pwrctrl->reg_dramc1_md32_vrf18_req_mask_b & 0x1) << 24) | |
| 280 | ((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) | |
| 281 | ((pwrctrl->reg_dramc0_md32_wakeup_mask & 0x1) << 26) | |
| 282 | ((pwrctrl->reg_dramc1_md32_wakeup_mask & 0x1) << 27)); |
| 283 | |
| 284 | /* SPM_SRC5_MASK */ |
| 285 | write32(&mtk_spm->spm_src5_mask, |
| 286 | ((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) | |
| 287 | ((pwrctrl->reg_mcusys_merge_ddr_en_mask_b & 0x1ff) << 9) | |
| 288 | ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 18) | |
| 289 | ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 19) | |
| 290 | ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 20) | |
| 291 | ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 21) | |
| 292 | ((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 22) | |
| 293 | ((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 23) | |
| 294 | ((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 24) | |
| 295 | ((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 25) | |
| 296 | ((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 26) | |
| 297 | ((pwrctrl->reg_pcie_ddr_en_mask_b & 0x1) << 27)); |
| 298 | |
| 299 | /* SPM_WAKEUP_EVENT_MASK */ |
| 300 | write32(&mtk_spm->spm_wakeup_event_mask, |
| 301 | ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0)); |
| 302 | |
| 303 | /* SPM_WAKEUP_EVENT_EXT_MASK */ |
| 304 | write32(&mtk_spm->spm_wakeup_event_ext_mask, |
| 305 | ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0)); |
| 306 | |
| 307 | /* Auto-gen End */ |
| 308 | } |
| 309 | |
| 310 | static void spm_register_init(void) |
| 311 | { |
| 312 | /* Enable register control */ |
| 313 | write32(&mtk_spm->poweron_config_set, |
| 314 | SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); |
| 315 | |
| 316 | /* Init power control register */ |
| 317 | write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF); |
| 318 | write32(&mtk_spm->pcm_pwr_io_en, 0); |
| 319 | |
| 320 | /* Reset PCM */ |
| 321 | write32(&mtk_spm->pcm_con0, |
| 322 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB); |
| 323 | write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); |
| 324 | write32(&mtk_spm->pcm_con1, |
| 325 | SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB | |
| 326 | REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB | |
| 327 | REG_MD32_APB_INTERNAL_EN_LSB); |
| 328 | |
| 329 | /* Initial SPM CLK control register */ |
| 330 | setbits32(&mtk_spm->spm_clk_con, REG_SYSCLK1_SRC_MD2_SRCCLKENA); |
| 331 | |
| 332 | /* Clean wakeup event raw status */ |
| 333 | write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF); |
| 334 | |
| 335 | /* Clean ISR status */ |
| 336 | write32(&mtk_spm->spm_irq_mask, ISRM_ALL); |
| 337 | write32(&mtk_spm->spm_irq_sta, ISRC_ALL); |
| 338 | write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL); |
| 339 | |
| 340 | /* Init r7 with POWER_ON_VAL1 */ |
| 341 | write32(&mtk_spm->pcm_reg_data_ini, |
| 342 | read32(&mtk_spm->spm_power_on_val1)); |
| 343 | write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); |
| 344 | write32(&mtk_spm->pcm_pwr_io_en, 0); |
| 345 | |
| 346 | /* DDR EN de-bounce length to 5us */ |
| 347 | write32(&mtk_spm->ddr_en_dbc_con0, DDR_EN_DBC_CON0_DEF); |
| 348 | write32(&mtk_spm->ddr_en_dbc_con1, REG_ALL_DDR_EN_DBC_EN_LSB); |
| 349 | |
| 350 | /* Configure ARMPLL Control Mode for MCDI */ |
| 351 | write32(&mtk_spm->armpll_clk_sel, ARMPLL_CLK_SEL_DEF); |
| 352 | |
| 353 | /* Init for SPM Resource ACK */ |
| 354 | write32(&mtk_spm->spm_resource_ack_con0, SPM_RESOURCE_ACK_CON0_DEF); |
| 355 | write32(&mtk_spm->spm_resource_ack_con1, SPM_RESOURCE_ACK_CON1_DEF); |
| 356 | write32(&mtk_spm->spm_resource_ack_con2, SPM_RESOURCE_ACK_CON2_DEF); |
| 357 | write32(&mtk_spm->spm_resource_ack_con3, SPM_RESOURCE_ACK_CON3_DEF); |
| 358 | |
| 359 | /* Init VCORE DVFS Status */ |
| 360 | clrsetbits32(&mtk_spm->spm_dvfs_misc, |
| 361 | SPM_DVFS_FORCE_ENABLE_LSB, SPM_DVFSRC_ENABLE_LSB); |
| 362 | write32(&mtk_spm->spm_dvfs_level, SPM_DVFS_LEVEL_DEF); |
| 363 | write32(&mtk_spm->spm_dvs_dfs_level, SPM_DVS_DFS_LEVEL_DEF); |
| 364 | |
| 365 | write32(&mtk_spm->spm_ack_chk_sel_3, SPM_ACK_CHK_3_SEL_HW_S1); |
| 366 | write32(&mtk_spm->spm_ack_chk_timer_3, SPM_ACK_CHK_3_HW_S1_CNT); |
| 367 | |
| 368 | /* Apm hw s1 state monitor pause */ |
| 369 | clrsetbits32(&mtk_spm->spm_ack_chk_con_3, |
| 370 | SPM_ACK_CHK_3_CON_EN, |
| 371 | SPM_ACK_CHK_3_CON_HW_MODE_TRIG | |
| 372 | SPM_ACK_CHK_3_CON_CLR_ALL); |
| 373 | } |
| 374 | |
| 375 | static void spm_set_sysclk_settle(void) |
| 376 | { |
| 377 | write32(&mtk_spm->spm_clk_settle, SPM_SYSCLK_SETTLE); |
| 378 | } |
| 379 | |
| 380 | static void spm_code_swapping(void) |
| 381 | { |
| 382 | u32 mask; |
| 383 | |
| 384 | mask = read32(&mtk_spm->spm_wakeup_event_mask); |
| 385 | write32(&mtk_spm->spm_wakeup_event_mask, |
| 386 | mask & ~SPM_WAKEUP_EVENT_MASK_BIT0); |
| 387 | write32(&mtk_spm->spm_cpu_wakeup_event, 1); |
| 388 | write32(&mtk_spm->spm_cpu_wakeup_event, 0); |
| 389 | write32(&mtk_spm->spm_wakeup_event_mask, mask); |
| 390 | } |
| 391 | |
| 392 | static void spm_reset_and_init_pcm(void) |
| 393 | { |
| 394 | bool first_load_fw = true; |
| 395 | |
| 396 | /* Check the SPM FW is run or not */ |
| 397 | if (read32(&mtk_spm->md32pcm_cfgreg_sw_rstn) & |
| 398 | MD32PCM_CFGREG_SW_RSTN_RUN) |
| 399 | first_load_fw = false; |
| 400 | |
| 401 | if (!first_load_fw) { |
| 402 | spm_code_swapping(); |
| 403 | /* Backup PCM r0 -> SPM_POWER_ON_VAL0 before reset PCM */ |
| 404 | write32(&mtk_spm->spm_power_on_val0, |
| 405 | read32(&mtk_spm->pcm_reg0_data)); |
| 406 | } |
| 407 | |
| 408 | /* Disable r0 and r7 to control power */ |
| 409 | write32(&mtk_spm->pcm_pwr_io_en, 0); |
| 410 | |
| 411 | /* Disable pcm timer after leaving FW */ |
| 412 | clrsetbits32(&mtk_spm->pcm_con1, |
| 413 | RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); |
| 414 | |
| 415 | /* Reset PCM */ |
| 416 | write32(&mtk_spm->pcm_con0, |
| 417 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB); |
| 418 | write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); |
| 419 | |
| 420 | /* Init PCM_CON1 (disable PCM timer but keep PCM WDT setting) */ |
| 421 | clrsetbits32(&mtk_spm->pcm_con1, ~RG_PCM_WDT_WAKE_LSB, |
| 422 | SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB | |
| 423 | REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB | |
| 424 | REG_MD32_APB_INTERNAL_EN_LSB); |
| 425 | } |
| 426 | |
| 427 | static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm) |
| 428 | { |
| 429 | uintptr_t ptr; |
| 430 | u32 dmem_words; |
| 431 | u32 pmem_words; |
| 432 | u32 total_words; |
| 433 | u32 pmem_start; |
| 434 | u32 dmem_start; |
| 435 | |
| 436 | ptr = (uintptr_t)pcm->buf + SPM_SYSTEM_BASE_OFFSET; |
| 437 | pmem_words = pcm->desc.pmem_words; |
| 438 | total_words = pcm->desc.total_words; |
| 439 | dmem_words = total_words - pmem_words; |
| 440 | pmem_start = pcm->desc.pmem_start; |
| 441 | dmem_start = pcm->desc.dmem_start; |
| 442 | |
| 443 | printk(BIOS_DEBUG, "%s: ptr = %#lx, pmem/dmem words = %#x/%#x\n", |
| 444 | __func__, (long)ptr, pmem_words, dmem_words); |
| 445 | |
| 446 | /* DMA needs 16-byte aligned source data. */ |
| 447 | assert(ptr % 16 == 0); |
| 448 | /* Program/Data must also be 16-byte (4-word) aligned. */ |
| 449 | assert(pmem_words % 4 == 0); |
| 450 | assert(dmem_words % 4 == 0); |
| 451 | |
| 452 | write32(&mtk_spm->md32pcm_dma0_src, ptr); |
| 453 | write32(&mtk_spm->md32pcm_dma0_dst, pmem_start); |
| 454 | write32(&mtk_spm->md32pcm_dma0_wppt, pmem_words); |
| 455 | write32(&mtk_spm->md32pcm_dma0_wpto, dmem_start); |
| 456 | write32(&mtk_spm->md32pcm_dma0_count, total_words); |
| 457 | write32(&mtk_spm->md32pcm_dma0_con, MD32PCM_DMA0_CON_VAL); |
| 458 | write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL); |
| 459 | |
| 460 | setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); |
| 461 | } |
| 462 | |
| 463 | static void spm_init_pcm_register(void) |
| 464 | { |
| 465 | /* Init r0 with POWER_ON_VAL0 */ |
| 466 | write32(&mtk_spm->pcm_reg_data_ini, |
| 467 | read32(&mtk_spm->spm_power_on_val0)); |
| 468 | write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0); |
| 469 | write32(&mtk_spm->pcm_pwr_io_en, 0); |
| 470 | |
| 471 | /* Init r7 with POWER_ON_VAL1 */ |
| 472 | write32(&mtk_spm->pcm_reg_data_ini, |
| 473 | read32(&mtk_spm->spm_power_on_val1)); |
| 474 | write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); |
| 475 | write32(&mtk_spm->pcm_pwr_io_en, 0); |
| 476 | } |
| 477 | |
Roger Lu | a5f472b | 2020-07-10 15:29:31 +0800 | [diff] [blame] | 478 | static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) |
| 479 | { |
| 480 | u32 val, mask; |
| 481 | |
| 482 | /* Toggle event counter clear */ |
| 483 | setbits32(&mtk_spm->pcm_con1, |
| 484 | SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB); |
| 485 | |
| 486 | /* Toggle for reset SYS TIMER start point */ |
| 487 | setbits32(&mtk_spm->sys_timer_con, SYS_TIMER_START_EN_LSB); |
| 488 | |
| 489 | if (pwrctrl->timer_val_cust == 0) |
| 490 | val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX; |
| 491 | else |
| 492 | val = pwrctrl->timer_val_cust; |
| 493 | |
| 494 | write32(&mtk_spm->pcm_timer_val, val); |
| 495 | |
| 496 | /* Disable pcm timer */ |
| 497 | clrsetbits32(&mtk_spm->pcm_con1, |
| 498 | RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); |
| 499 | |
| 500 | /* Unmask AP wakeup source */ |
| 501 | if (pwrctrl->wake_src_cust == 0) |
| 502 | mask = pwrctrl->wake_src; |
| 503 | else |
| 504 | mask = pwrctrl->wake_src_cust; |
| 505 | |
| 506 | if (pwrctrl->reg_csyspwrreq_mask) |
| 507 | mask &= ~SPM_WAKEUP_EVENT_MASK_CSYSPWREQ_B; |
| 508 | |
| 509 | write32(&mtk_spm->spm_wakeup_event_mask, ~mask); |
| 510 | |
| 511 | /* Unmask SPM ISR (keep TWAM setting) */ |
| 512 | setbits32(&mtk_spm->spm_irq_mask, ISRM_RET_IRQ_AUX); |
| 513 | |
| 514 | /* Toggle event counter clear */ |
| 515 | clrsetbits32(&mtk_spm->pcm_con1, |
| 516 | SPM_EVENT_COUNTER_CLR_LSB, SPM_REGWR_CFG_KEY); |
| 517 | |
| 518 | /* Toggle for reset SYS TIMER start point */ |
| 519 | clrbits32(&mtk_spm->sys_timer_con, SYS_TIMER_START_EN_LSB); |
| 520 | } |
| 521 | |
| 522 | static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl) |
| 523 | { |
| 524 | u32 pcm_flags = pwrctrl->pcm_flags, pcm_flags1 = pwrctrl->pcm_flags1; |
| 525 | |
| 526 | /* Set PCM flags and data */ |
| 527 | if (pwrctrl->pcm_flags_cust_clr != 0) |
| 528 | pcm_flags &= ~pwrctrl->pcm_flags_cust_clr; |
| 529 | if (pwrctrl->pcm_flags_cust_set != 0) |
| 530 | pcm_flags |= pwrctrl->pcm_flags_cust_set; |
| 531 | if (pwrctrl->pcm_flags1_cust_clr != 0) |
| 532 | pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr; |
| 533 | if (pwrctrl->pcm_flags1_cust_set != 0) |
| 534 | pcm_flags1 |= pwrctrl->pcm_flags1_cust_set; |
| 535 | |
| 536 | write32(&mtk_spm->spm_sw_flag_0, pcm_flags); |
| 537 | write32(&mtk_spm->spm_sw_flag_1, pcm_flags1); |
| 538 | write32(&mtk_spm->spm_sw_rsv_7, pcm_flags); |
| 539 | write32(&mtk_spm->spm_sw_rsv_8, pcm_flags1); |
| 540 | } |
| 541 | |
| 542 | static void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl) |
| 543 | { |
| 544 | /* Waiting for loading SPMFW done*/ |
| 545 | while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0) |
| 546 | ; |
| 547 | |
| 548 | /* Init register to match PCM expectation */ |
| 549 | write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF); |
| 550 | write32(&mtk_spm->spm_bus_protect2_mask_b, |
| 551 | SPM_BUS_PROTECT2_MASK_B_DEF); |
| 552 | write32(&mtk_spm->pcm_reg_data_ini, 0); |
| 553 | |
| 554 | spm_set_pcm_flags(pwrctrl); |
| 555 | |
| 556 | /* Kick PCM to run (only toggle PCM_KICK) */ |
| 557 | setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); |
| 558 | |
| 559 | /* Reset md32pcm */ |
| 560 | setbits32(&mtk_spm->md32pcm_cfgreg_sw_rstn, |
| 561 | MD32PCM_CFGREG_SW_RSTN_RESET); |
| 562 | |
| 563 | /* Waiting for SPM init done */ |
| 564 | udelay(SPM_INIT_DONE_US); |
| 565 | } |
| 566 | |
| 567 | static void reset_spm(struct mtk_mcu *mcu) |
| 568 | { |
| 569 | struct dyna_load_pcm *pcm = (struct dyna_load_pcm *)mcu->priv; |
| 570 | |
| 571 | spm_parse_firmware(mcu); |
| 572 | spm_reset_and_init_pcm(); |
| 573 | spm_kick_im_to_fetch(pcm); |
| 574 | spm_init_pcm_register(); |
| 575 | spm_set_wakeup_event(&spm_init_ctrl); |
| 576 | spm_kick_pcm_to_run(&spm_init_ctrl); |
| 577 | } |
| 578 | |
| 579 | static struct mtk_mcu spm = { |
| 580 | .firmware_name = CONFIG_SPM_FIRMWARE, |
| 581 | .reset = reset_spm, |
| 582 | }; |
| 583 | |
| 584 | int spm_init(void) |
| 585 | { |
| 586 | struct dyna_load_pcm pcm; |
| 587 | struct stopwatch sw; |
| 588 | |
| 589 | stopwatch_init(&sw); |
| 590 | |
| 591 | spm_register_init(); |
| 592 | spm_set_power_control(&spm_init_ctrl); |
| 593 | spm_set_sysclk_settle(); |
| 594 | |
| 595 | spm.load_buffer = _dram_dma; |
| 596 | spm.buffer_size = REGION_SIZE(dram_dma); |
| 597 | spm.priv = (void *)&pcm; |
| 598 | |
| 599 | if (mtk_init_mcu(&spm)) { |
| 600 | printk(BIOS_ERR, "SPM: %s: failed in mtk_init_mcu\n", __func__); |
| 601 | return -1; |
| 602 | } |
| 603 | |
| 604 | printk(BIOS_INFO, "SPM: %s done in %ld msecs, spm pc = %#x\n", |
| 605 | __func__, stopwatch_duration_msecs(&sw), |
| 606 | read32(&mtk_spm->md32pcm_pc)); |
| 607 | |
| 608 | return 0; |
| 609 | } |