Weiyi Lu | a4cad36 | 2020-05-13 10:01:14 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Weiyi Lu | 26d1652 | 2020-06-22 16:21:58 +0800 | [diff] [blame] | 3 | #include <console/console.h> |
Weiyi Lu | a4cad36 | 2020-05-13 10:01:14 +0800 | [diff] [blame] | 4 | #include <device/mmio.h> |
| 5 | #include <delay.h> |
| 6 | #include <stddef.h> |
Weiyi Lu | 26d1652 | 2020-06-22 16:21:58 +0800 | [diff] [blame] | 7 | #include <timer.h> |
Weiyi Lu | a4cad36 | 2020-05-13 10:01:14 +0800 | [diff] [blame] | 8 | |
| 9 | #include <soc/addressmap.h> |
| 10 | #include <soc/infracfg.h> |
| 11 | #include <soc/mcucfg.h> |
| 12 | #include <soc/pll.h> |
Weiyi Lu | dac4fa6 | 2020-10-15 14:25:01 +0800 | [diff] [blame] | 13 | #include <soc/wdt.h> |
Weiyi Lu | a4cad36 | 2020-05-13 10:01:14 +0800 | [diff] [blame] | 14 | |
| 15 | enum mux_id { |
| 16 | TOP_AXI_SEL, |
| 17 | TOP_SPM_SEL, |
| 18 | TOP_SCP_SEL, |
| 19 | TOP_BUS_AXIMEM_SEL, |
| 20 | TOP_DISP_SEL, |
| 21 | TOP_MDP_SEL, |
| 22 | TOP_IMG1_SEL, |
| 23 | TOP_IMG2_SEL, |
| 24 | TOP_IPE_SEL, |
| 25 | TOP_DPE_SEL, |
| 26 | TOP_CAM_SEL, |
| 27 | TOP_CCU_SEL, |
| 28 | TOP_DSP_SEL, |
| 29 | TOP_DSP7_SEL, |
| 30 | TOP_MFG_REF_SEL, |
| 31 | TOP_MFG_PLL_SEL, |
| 32 | TOP_CAMTG_SEL, |
| 33 | TOP_CAMTG2_SEL, |
| 34 | TOP_CAMTG3_SEL, |
| 35 | TOP_CAMTG4_SEL, |
| 36 | TOP_CAMTG5_SEL, |
| 37 | TOP_CAMTG6_SEL, |
| 38 | TOP_UART_SEL, |
| 39 | TOP_SPI_SEL, |
| 40 | TOP_MSDC50_0_HCLK_SEL, |
| 41 | TOP_MSDC50_0_SEL, |
| 42 | TOP_MSDC30_1_SEL, |
| 43 | TOP_MSDC30_2_SEL, |
| 44 | TOP_AUDIO_SEL, |
| 45 | TOP_AUD_INTBUS_SEL, |
| 46 | TOP_PWRAP_ULPOSC_SEL, |
| 47 | TOP_ATB_SEL, |
| 48 | TOP_PWRMCU_SEL, |
| 49 | TOP_DPI_SEL, |
| 50 | TOP_SCAM_SEL, |
| 51 | TOP_DISP_PWM_SEL, |
| 52 | TOP_USB_TOP_SEL, |
| 53 | TOP_SSUSB_XHCI_SEL, |
| 54 | TOP_I2C_SEL, |
| 55 | TOP_SENINF_SEL, |
| 56 | TOP_SENINF1_SEL, |
| 57 | TOP_SENINF2_SEL, |
| 58 | TOP_SENINF3_SEL, |
| 59 | TOP_TL_SEL, |
| 60 | TOP_DXCC_SEL, |
| 61 | TOP_AUD_ENGEN1_SEL, |
| 62 | TOP_AUD_ENGEN2_SEL, |
| 63 | TOP_AES_UFSFDE_SEL, |
| 64 | TOP_UFS_SEL, |
| 65 | TOP_AUD_1_SEL, |
| 66 | TOP_AUD_2_SEL, |
| 67 | TOP_ADSP_SEL, |
| 68 | TOP_DPMAIF_MAIN_SEL, |
| 69 | TOP_VENC_SEL, |
| 70 | TOP_VDEC_SEL, |
| 71 | TOP_CAMTM_SEL, |
| 72 | TOP_PWM_SEL, |
| 73 | TOP_AUDIO_H_SEL, |
| 74 | TOP_SPMI_MST_SEL, |
| 75 | TOP_DVFSRC_SEL, |
| 76 | TOP_AES_MSDCFDE_SEL, |
| 77 | TOP_MCUPM_SEL, |
| 78 | TOP_SFLASH_SEL, |
| 79 | TOP_NR_MUX |
| 80 | }; |
| 81 | |
| 82 | #define MUX(_id, _reg, _mux_shift, _mux_width) \ |
| 83 | [_id] = { \ |
| 84 | .reg = &mtk_topckgen->_reg, \ |
| 85 | .set_reg = &mtk_topckgen->_reg##_set, \ |
| 86 | .clr_reg = &mtk_topckgen->_reg##_clr, \ |
| 87 | .mux_shift = _mux_shift, \ |
| 88 | .mux_width = _mux_width, \ |
| 89 | .upd_reg = NULL, \ |
| 90 | .upd_shift = 0, \ |
| 91 | } |
| 92 | |
| 93 | #define MUX_UPD(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\ |
| 94 | [_id] = { \ |
| 95 | .reg = &mtk_topckgen->_reg, \ |
| 96 | .set_reg = &mtk_topckgen->_reg##_set, \ |
| 97 | .clr_reg = &mtk_topckgen->_reg##_clr, \ |
| 98 | .mux_shift = _mux_shift, \ |
| 99 | .mux_width = _mux_width, \ |
| 100 | .upd_reg = &mtk_topckgen->_upd_reg, \ |
| 101 | .upd_shift = _upd_shift, \ |
| 102 | } |
| 103 | |
| 104 | static const struct mux muxes[] = { |
| 105 | /* CLK_CFG_0 */ |
| 106 | MUX_UPD(TOP_AXI_SEL, clk_cfg_0, 0, 3, clk_cfg_update, 0), |
| 107 | MUX_UPD(TOP_SPM_SEL, clk_cfg_0, 8, 2, clk_cfg_update, 1), |
| 108 | MUX_UPD(TOP_SCP_SEL, clk_cfg_0, 16, 3, clk_cfg_update, 2), |
| 109 | MUX_UPD(TOP_BUS_AXIMEM_SEL, clk_cfg_0, 24, 3, clk_cfg_update, 3), |
| 110 | /* CLK_CFG_1 */ |
| 111 | MUX_UPD(TOP_DISP_SEL, clk_cfg_1, 0, 4, clk_cfg_update, 4), |
| 112 | MUX_UPD(TOP_MDP_SEL, clk_cfg_1, 8, 4, clk_cfg_update, 5), |
| 113 | MUX_UPD(TOP_IMG1_SEL, clk_cfg_1, 16, 4, clk_cfg_update, 6), |
| 114 | MUX_UPD(TOP_IMG2_SEL, clk_cfg_1, 24, 4, clk_cfg_update, 7), |
| 115 | /* CLK_CFG_2 */ |
| 116 | MUX_UPD(TOP_IPE_SEL, clk_cfg_2, 0, 4, clk_cfg_update, 8), |
| 117 | MUX_UPD(TOP_DPE_SEL, clk_cfg_2, 8, 3, clk_cfg_update, 9), |
| 118 | MUX_UPD(TOP_CAM_SEL, clk_cfg_2, 16, 4, clk_cfg_update, 10), |
| 119 | MUX_UPD(TOP_CCU_SEL, clk_cfg_2, 24, 4, clk_cfg_update, 11), |
| 120 | /* CLK_CFG_3 */ |
| 121 | MUX_UPD(TOP_DSP_SEL, clk_cfg_3, 0, 3, clk_cfg_update, 12), |
| 122 | /* CLK_CFG_4 */ |
| 123 | MUX_UPD(TOP_DSP7_SEL, clk_cfg_4, 0, 3, clk_cfg_update, 16), |
| 124 | MUX_UPD(TOP_MFG_REF_SEL, clk_cfg_4, 16, 2, clk_cfg_update, 18), |
| 125 | MUX(TOP_MFG_PLL_SEL, clk_cfg_4, 18, 1), |
| 126 | MUX_UPD(TOP_CAMTG_SEL, clk_cfg_4, 24, 3, clk_cfg_update, 19), |
| 127 | /* CLK_CFG_5 */ |
| 128 | MUX_UPD(TOP_CAMTG2_SEL, clk_cfg_5, 0, 3, clk_cfg_update, 20), |
| 129 | MUX_UPD(TOP_CAMTG3_SEL, clk_cfg_5, 8, 3, clk_cfg_update, 21), |
| 130 | MUX_UPD(TOP_CAMTG4_SEL, clk_cfg_5, 16, 3, clk_cfg_update, 22), |
| 131 | MUX_UPD(TOP_CAMTG5_SEL, clk_cfg_5, 24, 3, clk_cfg_update, 23), |
| 132 | /* CLK_CFG_6 */ |
| 133 | MUX_UPD(TOP_CAMTG6_SEL, clk_cfg_6, 0, 3, clk_cfg_update, 24), |
| 134 | MUX_UPD(TOP_UART_SEL, clk_cfg_6, 8, 1, clk_cfg_update, 25), |
| 135 | MUX_UPD(TOP_SPI_SEL, clk_cfg_6, 16, 2, clk_cfg_update, 26), |
| 136 | MUX_UPD(TOP_MSDC50_0_HCLK_SEL, clk_cfg_6, 24, 2, clk_cfg_update, 27), |
| 137 | /* CLK_CFG_7 */ |
| 138 | MUX_UPD(TOP_MSDC50_0_SEL, clk_cfg_7, 0, 3, clk_cfg_update, 28), |
| 139 | MUX_UPD(TOP_MSDC30_1_SEL, clk_cfg_7, 8, 3, clk_cfg_update, 29), |
| 140 | MUX_UPD(TOP_MSDC30_2_SEL, clk_cfg_7, 16, 3, clk_cfg_update, 30), |
| 141 | MUX_UPD(TOP_AUDIO_SEL, clk_cfg_7, 24, 2, clk_cfg_update1, 0), |
| 142 | /* CLK_CFG_8 */ |
| 143 | MUX_UPD(TOP_AUD_INTBUS_SEL, clk_cfg_8, 0, 2, clk_cfg_update1, 1), |
| 144 | MUX_UPD(TOP_PWRAP_ULPOSC_SEL, clk_cfg_8, 8, 3, clk_cfg_update1, 2), |
| 145 | MUX_UPD(TOP_ATB_SEL, clk_cfg_8, 16, 2, clk_cfg_update1, 3), |
| 146 | MUX_UPD(TOP_PWRMCU_SEL, clk_cfg_8, 24, 3, clk_cfg_update1, 4), |
| 147 | /* CLK_CFG_9 */ |
| 148 | MUX_UPD(TOP_DPI_SEL, clk_cfg_9, 0, 3, clk_cfg_update1, 5), |
| 149 | MUX_UPD(TOP_SCAM_SEL, clk_cfg_9, 8, 1, clk_cfg_update1, 6), |
| 150 | MUX_UPD(TOP_DISP_PWM_SEL, clk_cfg_9, 16, 3, clk_cfg_update1, 7), |
| 151 | MUX_UPD(TOP_USB_TOP_SEL, clk_cfg_9, 24, 2, clk_cfg_update1, 8), |
| 152 | /* CLK_CFG_10 */ |
| 153 | MUX_UPD(TOP_SSUSB_XHCI_SEL, clk_cfg_10, 0, 2, clk_cfg_update1, 9), |
| 154 | MUX_UPD(TOP_I2C_SEL, clk_cfg_10, 8, 2, clk_cfg_update1, 10), |
| 155 | MUX_UPD(TOP_SENINF_SEL, clk_cfg_10, 16, 3, clk_cfg_update1, 11), |
| 156 | MUX_UPD(TOP_SENINF1_SEL, clk_cfg_10, 24, 3, clk_cfg_update1, 12), |
| 157 | /* CLK_CFG_11 */ |
| 158 | MUX_UPD(TOP_SENINF2_SEL, clk_cfg_11, 0, 3, clk_cfg_update1, 13), |
| 159 | MUX_UPD(TOP_SENINF3_SEL, clk_cfg_11, 8, 3, clk_cfg_update1, 14), |
| 160 | MUX_UPD(TOP_TL_SEL, clk_cfg_11, 16, 2, clk_cfg_update1, 15), |
| 161 | MUX_UPD(TOP_DXCC_SEL, clk_cfg_11, 24, 2, clk_cfg_update1, 16), |
| 162 | /* CLK_CFG_12 */ |
| 163 | MUX_UPD(TOP_AUD_ENGEN1_SEL, clk_cfg_12, 0, 2, clk_cfg_update1, 17), |
| 164 | MUX_UPD(TOP_AUD_ENGEN2_SEL, clk_cfg_12, 8, 2, clk_cfg_update1, 18), |
| 165 | MUX_UPD(TOP_AES_UFSFDE_SEL, clk_cfg_12, 16, 3, clk_cfg_update1, 19), |
| 166 | MUX_UPD(TOP_UFS_SEL, clk_cfg_12, 24, 3, clk_cfg_update1, 20), |
| 167 | /* CLK_CFG_13 */ |
| 168 | MUX_UPD(TOP_AUD_1_SEL, clk_cfg_13, 0, 1, clk_cfg_update1, 21), |
| 169 | MUX_UPD(TOP_AUD_2_SEL, clk_cfg_13, 8, 1, clk_cfg_update1, 22), |
| 170 | MUX_UPD(TOP_ADSP_SEL, clk_cfg_13, 16, 3, clk_cfg_update1, 23), |
| 171 | MUX_UPD(TOP_DPMAIF_MAIN_SEL, clk_cfg_13, 24, 3, clk_cfg_update1, 24), |
| 172 | /* CLK_CFG_14 */ |
| 173 | MUX_UPD(TOP_VENC_SEL, clk_cfg_14, 0, 4, clk_cfg_update1, 25), |
| 174 | MUX_UPD(TOP_VDEC_SEL, clk_cfg_14, 8, 4, clk_cfg_update1, 26), |
| 175 | MUX_UPD(TOP_CAMTM_SEL, clk_cfg_14, 16, 2, clk_cfg_update1, 27), |
| 176 | MUX_UPD(TOP_PWM_SEL, clk_cfg_14, 24, 1, clk_cfg_update1, 28), |
| 177 | /* CLK_CFG_15 */ |
| 178 | MUX_UPD(TOP_AUDIO_H_SEL, clk_cfg_15, 0, 2, clk_cfg_update1, 29), |
| 179 | MUX_UPD(TOP_SPMI_MST_SEL, clk_cfg_15, 8, 3, clk_cfg_update1, 30), |
| 180 | MUX_UPD(TOP_DVFSRC_SEL, clk_cfg_15, 16, 1, clk_cfg_update2, 0), |
| 181 | MUX_UPD(TOP_AES_MSDCFDE_SEL, clk_cfg_15, 24, 3, clk_cfg_update2, 1), |
| 182 | /* CLK_CFG_16 */ |
| 183 | MUX_UPD(TOP_MCUPM_SEL, clk_cfg_16, 0, 2, clk_cfg_update2, 2), |
| 184 | MUX_UPD(TOP_SFLASH_SEL, clk_cfg_16, 8, 2, clk_cfg_update2, 3), |
| 185 | }; |
| 186 | |
| 187 | struct mux_sel { |
| 188 | enum mux_id id; |
| 189 | u32 sel; |
| 190 | }; |
| 191 | |
| 192 | static const struct mux_sel mux_sels[] = { |
| 193 | /* CLK_CFG_0 */ |
| 194 | { .id = TOP_AXI_SEL, .sel = 2 }, /* 2: mainpll_d7_d2 */ |
| 195 | { .id = TOP_SPM_SEL, .sel = 2 }, /* 2: mainpll_d7_d4 */ |
| 196 | { .id = TOP_SCP_SEL, .sel = 0 }, /* 0: clk26m */ |
| 197 | { .id = TOP_BUS_AXIMEM_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */ |
| 198 | /* CLK_CFG_1 */ |
| 199 | { .id = TOP_DISP_SEL, .sel = 8 }, /* 8: mainpll_d4 */ |
| 200 | { .id = TOP_MDP_SEL, .sel = 8 }, /* 8: tvdpll_ck */ |
| 201 | { .id = TOP_IMG1_SEL, .sel = 1 }, /* 1: univpll_d4 */ |
| 202 | { .id = TOP_IMG2_SEL, .sel = 1 }, /* 1: univpll_d4 */ |
| 203 | /* CLK_CFG_2 */ |
| 204 | { .id = TOP_IPE_SEL, .sel = 1 }, /* 1: mainpll_d4 */ |
| 205 | { .id = TOP_DPE_SEL, .sel = 1 }, /* 1: mainpll_d4 */ |
| 206 | { .id = TOP_CAM_SEL, .sel = 3 }, /* 3: univpll_d4 */ |
| 207 | { .id = TOP_CCU_SEL, .sel = 8 }, /* 8: univpll_d5 */ |
| 208 | /* CLK_CFG_3 */ |
| 209 | { .id = TOP_DSP_SEL, .sel = 1 }, /* 1: univpll_d6_d2 */ |
| 210 | /* CLK_CFG_4 */ |
| 211 | { .id = TOP_DSP7_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */ |
| 212 | { .id = TOP_MFG_REF_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */ |
| 213 | { .id = TOP_MFG_PLL_SEL, .sel = 1 }, /* 1: mfgpll */ |
| 214 | { .id = TOP_CAMTG_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ |
| 215 | /* CLK_CFG_5 */ |
| 216 | { .id = TOP_CAMTG2_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ |
| 217 | { .id = TOP_CAMTG3_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ |
| 218 | { .id = TOP_CAMTG4_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ |
| 219 | { .id = TOP_CAMTG5_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ |
| 220 | /* CLK_CFG_6 */ |
| 221 | { .id = TOP_CAMTG6_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */ |
| 222 | { .id = TOP_UART_SEL, .sel = 0 }, /* 0: clk26m */ |
| 223 | { .id = TOP_SPI_SEL, .sel = 1 }, /* 1: mainpll_d5_d4 */ |
| 224 | { .id = TOP_MSDC50_0_HCLK_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */ |
| 225 | /* CLK_CFG_7 */ |
| 226 | { .id = TOP_MSDC50_0_SEL, .sel = 1 }, /* 1: msdcpll_ck */ |
| 227 | { .id = TOP_MSDC30_1_SEL, .sel = 4 }, /* 4: msdcpll_d2 */ |
| 228 | { .id = TOP_MSDC30_2_SEL, .sel = 4 }, /* 4: msdcpll_d2 */ |
| 229 | { .id = TOP_AUDIO_SEL, .sel = 0 }, /* 0: clk26m */ |
| 230 | /* CLK_CFG_8 */ |
| 231 | { .id = TOP_AUD_INTBUS_SEL, .sel = 1 }, /* 1: mainpll_d4_d4 */ |
| 232 | { .id = TOP_PWRAP_ULPOSC_SEL, .sel = 0 }, /* 0: osc_d10 */ |
| 233 | { .id = TOP_ATB_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */ |
| 234 | { .id = TOP_PWRMCU_SEL, .sel = 3 }, /* 3: mainpll_d4_d2 */ |
| 235 | /* CLK_CFG_9 */ |
| 236 | { .id = TOP_DPI_SEL, .sel = 1 }, /* 1: tvdpll_d2 */ |
| 237 | { .id = TOP_SCAM_SEL, .sel = 1 }, /* 1: mainpll_d5_d4 */ |
| 238 | { .id = TOP_DISP_PWM_SEL, .sel = 0 }, /* 0: clk26m */ |
| 239 | { .id = TOP_USB_TOP_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */ |
| 240 | /* CLK_CFG_10 */ |
| 241 | { .id = TOP_SSUSB_XHCI_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */ |
| 242 | { .id = TOP_I2C_SEL, .sel = 2 }, /* 2: univpll_d5_d4 */ |
| 243 | { .id = TOP_SENINF_SEL, .sel = 4 }, /* 4: univpll_d7 */ |
| 244 | { .id = TOP_SENINF1_SEL, .sel = 4 }, /* 4: univpll_d7 */ |
| 245 | /* CLK_CFG_11 */ |
| 246 | { .id = TOP_SENINF2_SEL, .sel = 4 }, /* 4: univpll_d7 */ |
| 247 | { .id = TOP_SENINF3_SEL, .sel = 4 }, /* 4: univpll_d7 */ |
| 248 | { .id = TOP_TL_SEL, .sel = 1 }, /* 1: univpll_192m_d2 */ |
| 249 | { .id = TOP_DXCC_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */ |
| 250 | /* CLK_CFG_12 */ |
| 251 | { .id = TOP_AUD_ENGEN1_SEL, .sel = 2 }, /* 2: apll1_d4 */ |
| 252 | { .id = TOP_AUD_ENGEN2_SEL, .sel = 2 }, /* 2: apll2_d4 */ |
| 253 | { .id = TOP_AES_UFSFDE_SEL, .sel = 6 }, /* 6: univpll_d6 */ |
| 254 | { .id = TOP_UFS_SEL, .sel = 6 }, /* 6: msdcpll_d2 */ |
| 255 | /* CLK_CFG_13 */ |
| 256 | { .id = TOP_AUD_1_SEL, .sel = 1 }, /* 1: apll1_ck */ |
| 257 | { .id = TOP_AUD_2_SEL, .sel = 1 }, /* 1: apll2_ck */ |
| 258 | { .id = TOP_ADSP_SEL, .sel = 7 }, /* 7: adsppll_ck */ |
| 259 | { .id = TOP_DPMAIF_MAIN_SEL, .sel = 3 }, /* 3: mainpll_d4_d2 */ |
| 260 | /* CLK_CFG_14 */ |
| 261 | { .id = TOP_VENC_SEL, .sel = 14 }, /* 14: univpll_d5_d2 */ |
| 262 | { .id = TOP_VDEC_SEL, .sel = 4 }, /* 4: mainpll_d5_d2 */ |
| 263 | { .id = TOP_CAMTM_SEL, .sel = 2 }, /* 2: univpll_d6_d2 */ |
| 264 | { .id = TOP_PWM_SEL, .sel = 0 }, /* 0: clk26m */ |
| 265 | /* CLK_CFG_15 */ |
| 266 | { .id = TOP_AUDIO_H_SEL, .sel = 3 }, /* 3: apll2_ck */ |
| 267 | { .id = TOP_SPMI_MST_SEL, .sel = 0 }, /* 0: clk26m */ |
| 268 | { .id = TOP_DVFSRC_SEL, .sel = 0 }, /* 0: clk26m */ |
| 269 | { .id = TOP_AES_MSDCFDE_SEL, .sel = 5 }, /* 5: univpll_d6 */ |
| 270 | /* CLK_CFG_16 */ |
| 271 | { .id = TOP_MCUPM_SEL, .sel = 2 }, /* 2: mainpll_d6_d2 */ |
| 272 | { .id = TOP_SFLASH_SEL, .sel = 1 }, /* 1: mainpll_d7_d8 */ |
| 273 | }; |
| 274 | |
| 275 | enum pll_id { |
| 276 | APMIXED_ARMPLL_LL, |
| 277 | APMIXED_ARMPLL_BL, |
| 278 | APMIXED_CCIPLL, |
| 279 | APMIXED_MAINPLL, |
| 280 | APMIXED_UNIVPLL, |
| 281 | APMIXED_USBPLL, |
| 282 | APMIXED_MSDCPLL, |
| 283 | APMIXED_MMPLL, |
| 284 | APMIXED_ADSPPLL, |
| 285 | APMIXED_MFGPLL, |
| 286 | APMIXED_TVDPLL, |
| 287 | APMIXED_APLL1, |
| 288 | APMIXED_APLL2, |
| 289 | APMIXED_PLL_MAX |
| 290 | }; |
| 291 | |
| 292 | const u32 pll_div_rate[] = { |
| 293 | 3800UL * MHz, |
| 294 | 1900 * MHz, |
| 295 | 950 * MHz, |
| 296 | 475 * MHz, |
| 297 | 237500 * KHz, |
| 298 | 0, |
| 299 | }; |
| 300 | |
| 301 | static const struct pll plls[] = { |
| 302 | PLL(APMIXED_ARMPLL_LL, armpll_ll_con0, armpll_ll_con3, |
| 303 | NO_RSTB_SHIFT, 22, armpll_ll_con1, 24, armpll_ll_con1, 0, |
| 304 | pll_div_rate), |
| 305 | PLL(APMIXED_ARMPLL_BL, armpll_bl0_con0, armpll_bl_con3, |
| 306 | NO_RSTB_SHIFT, 22, armpll_bl_con1, 24, armpll_bl_con1, 0, |
| 307 | pll_div_rate), |
| 308 | PLL(APMIXED_CCIPLL, ccipll_con0, ccipll_con3, |
| 309 | NO_RSTB_SHIFT, 22, ccipll_con1, 24, ccipll_con1, 0, |
| 310 | pll_div_rate), |
| 311 | PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_con3, |
| 312 | 23, 22, mainpll_con1, 24, mainpll_con1, 0, |
| 313 | pll_div_rate), |
| 314 | PLL(APMIXED_UNIVPLL, univpll_con0, univpll_con3, |
| 315 | 23, 22, univpll_con1, 24, univpll_con1, 0, |
| 316 | pll_div_rate), |
| 317 | PLL(APMIXED_USBPLL, usbpll_con0, usbpll_con2, |
| 318 | NO_RSTB_SHIFT, 22, usbpll_con0, 24, usbpll_con0, 0, |
| 319 | pll_div_rate), |
| 320 | PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_con3, |
| 321 | NO_RSTB_SHIFT, 22, msdcpll_con1, 24, msdcpll_con1, 0, |
| 322 | pll_div_rate), |
| 323 | PLL(APMIXED_MMPLL, mmpll_con0, mmpll_con3, |
| 324 | 23, 22, mmpll_con1, 24, mmpll_con1, 0, |
| 325 | pll_div_rate), |
| 326 | PLL(APMIXED_ADSPPLL, adsppll_con0, adsppll_con3, |
| 327 | NO_RSTB_SHIFT, 22, adsppll_con1, 24, adsppll_con1, 0, |
| 328 | pll_div_rate), |
| 329 | PLL(APMIXED_MFGPLL, mfgpll_con0, mfgpll_con3, |
| 330 | NO_RSTB_SHIFT, 22, mfgpll_con1, 24, mfgpll_con1, 0, |
| 331 | pll_div_rate), |
| 332 | PLL(APMIXED_TVDPLL, tvdpll_con0, tvdpll_con3, |
| 333 | NO_RSTB_SHIFT, 22, tvdpll_con1, 24, tvdpll_con1, 0, |
| 334 | pll_div_rate), |
| 335 | PLL(APMIXED_APLL1, apll1_con0, apll1_con4, |
| 336 | NO_RSTB_SHIFT, 32, apll1_con1, 24, apll1_con2, 0, |
| 337 | pll_div_rate), |
| 338 | PLL(APMIXED_APLL2, apll2_con0, apll2_con4, |
| 339 | NO_RSTB_SHIFT, 32, apll2_con1, 24, apll2_con2, 0, |
| 340 | pll_div_rate), |
| 341 | }; |
| 342 | |
| 343 | struct rate { |
| 344 | enum pll_id id; |
| 345 | u32 rate; |
| 346 | }; |
| 347 | |
| 348 | static const struct rate rates[] = { |
| 349 | { .id = APMIXED_ARMPLL_LL, .rate = ARMPLL_LL_HZ }, |
| 350 | { .id = APMIXED_ARMPLL_BL, .rate = ARMPLL_BL_HZ }, |
| 351 | { .id = APMIXED_CCIPLL, .rate = CCIPLL_HZ }, |
| 352 | { .id = APMIXED_MAINPLL, .rate = MAINPLL_HZ }, |
| 353 | { .id = APMIXED_UNIVPLL, .rate = UNIVPLL_HZ }, |
| 354 | { .id = APMIXED_USBPLL, .rate = USBPLL_HZ }, |
| 355 | { .id = APMIXED_MSDCPLL, .rate = MSDCPLL_HZ }, |
| 356 | { .id = APMIXED_MMPLL, .rate = MMPLL_HZ }, |
| 357 | { .id = APMIXED_ADSPPLL, .rate = ADSPPLL_HZ }, |
| 358 | { .id = APMIXED_MFGPLL, .rate = MFGPLL_HZ }, |
| 359 | { .id = APMIXED_TVDPLL, .rate = TVDPLL_HZ }, |
| 360 | { .id = APMIXED_APLL1, .rate = APLL1_HZ }, |
| 361 | { .id = APMIXED_APLL2, .rate = APLL2_HZ }, |
| 362 | }; |
| 363 | |
| 364 | void pll_set_pcw_change(const struct pll *pll) |
| 365 | { |
| 366 | setbits32(pll->div_reg, PLL_PCW_CHG); |
| 367 | } |
| 368 | |
| 369 | void mt_pll_init(void) |
| 370 | { |
| 371 | int i; |
| 372 | |
| 373 | /* enable clock square1 low-pass filter */ |
| 374 | setbits32(&mtk_apmixed->ap_pll_con0, 0x2); |
| 375 | |
| 376 | /* reduce PLL current */ |
| 377 | SET32_BITFIELDS(&mtk_apmixed->ap_pllgp1_con1, PLLGP1_LVRREF, 1); |
| 378 | SET32_BITFIELDS(&mtk_apmixed->ap_pllgp2_con1, PLLGP2_LVRREF, 1); |
| 379 | |
| 380 | /* xPLL PWR ON */ |
| 381 | for (i = 0; i < APMIXED_PLL_MAX; i++) |
| 382 | setbits32(plls[i].pwr_reg, PLL_PWR_ON); |
| 383 | |
| 384 | udelay(PLL_PWR_ON_DELAY); |
| 385 | |
| 386 | /* xPLL ISO Disable */ |
| 387 | for (i = 0; i < APMIXED_PLL_MAX; i++) |
| 388 | clrbits32(plls[i].pwr_reg, PLL_ISO); |
| 389 | |
| 390 | udelay(PLL_ISO_DELAY); |
| 391 | |
| 392 | /* xPLL Frequency Set */ |
| 393 | for (i = 0; i < ARRAY_SIZE(rates); i++) |
| 394 | pll_set_rate(&plls[rates[i].id], rates[i].rate); |
| 395 | |
Weiyi Lu | 92d5993 | 2020-08-19 10:53:26 +0800 | [diff] [blame] | 396 | /* AUDPLL Tuner Frequency Set */ |
| 397 | write32(&mtk_apmixed->apll1_tuner_con0, read32(&mtk_apmixed->apll1_con2) + 1); |
| 398 | write32(&mtk_apmixed->apll2_tuner_con0, read32(&mtk_apmixed->apll2_con2) + 1); |
| 399 | |
Weiyi Lu | a4cad36 | 2020-05-13 10:01:14 +0800 | [diff] [blame] | 400 | /* xPLL Frequency Enable */ |
| 401 | for (i = 0; i < APMIXED_PLL_MAX; i++) { |
| 402 | if (i == APMIXED_USBPLL) |
| 403 | setbits32(plls[APMIXED_USBPLL].pwr_reg, USBPLL_EN); |
| 404 | else |
| 405 | setbits32(plls[i].reg, PLL_EN); |
| 406 | } |
| 407 | |
| 408 | /* wait for PLL stable */ |
| 409 | udelay(PLL_EN_DELAY); |
| 410 | |
| 411 | /* xPLL DIV Enable & RSTB */ |
| 412 | for (i = 0; i < APMIXED_PLL_MAX; i++) { |
| 413 | if (plls[i].rstb_shift != NO_RSTB_SHIFT) { |
| 414 | setbits32(plls[i].reg, PLL_DIV_EN); |
| 415 | setbits32(plls[i].reg, 1 << plls[i].rstb_shift); |
| 416 | } |
| 417 | } |
| 418 | |
| 419 | /* MCUCFG CLKMUX */ |
Rex-BC Chen | 7d9bd17 | 2021-11-11 15:45:27 +0800 | [diff] [blame] | 420 | clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); |
| 421 | clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); |
| 422 | clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); |
Weiyi Lu | a4cad36 | 2020-05-13 10:01:14 +0800 | [diff] [blame] | 423 | |
Rex-BC Chen | 7d9bd17 | 2021-11-11 15:45:27 +0800 | [diff] [blame] | 424 | clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); |
| 425 | clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); |
| 426 | clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); |
Weiyi Lu | a4cad36 | 2020-05-13 10:01:14 +0800 | [diff] [blame] | 427 | |
| 428 | /* enable infrasys DCM */ |
| 429 | setbits32(&mt8192_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); |
| 430 | |
mtk15698 | 70ba37c | 2020-08-21 17:25:49 +0800 | [diff] [blame] | 431 | /* dcm_infracfg_ao_aximem_bus_dcm */ |
| 432 | clrsetbits32(&mt8192_infracfg->infra_aximem_idle_bit_en_0, |
| 433 | INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK, |
| 434 | INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON); |
| 435 | /* dcm_infracfg_ao_infra_bus_dcm */ |
| 436 | clrsetbits32(&mt8192_infracfg->infra_bus_dcm_ctrl, |
| 437 | INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK, |
| 438 | INFRACFG_AO_INFRA_BUS_DCM_REG0_ON); |
| 439 | /* dcm_infracfg_ao_infra_conn_bus_dcm */ |
| 440 | clrsetbits32(&mt8192_infracfg->module_sw_cg_2_set, |
| 441 | INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK, |
| 442 | INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_ON); |
| 443 | clrsetbits32(&mt8192_infracfg->module_sw_cg_2_clr, |
| 444 | INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK, |
| 445 | INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_ON); |
| 446 | /* dcm_infracfg_ao_infra_rx_p2p_dcm */ |
| 447 | clrsetbits32(&mt8192_infracfg->p2p_rx_clk_on, |
| 448 | INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK, |
| 449 | INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON); |
| 450 | /* dcm_infracfg_ao_peri_bus_dcm */ |
| 451 | clrsetbits32(&mt8192_infracfg->peri_bus_dcm_ctrl, |
| 452 | INFRACFG_AO_PERI_BUS_DCM_REG0_MASK, |
| 453 | INFRACFG_AO_PERI_BUS_DCM_REG0_ON); |
| 454 | /* dcm_infracfg_ao_peri_module_dcm */ |
| 455 | clrsetbits32(&mt8192_infracfg->peri_bus_dcm_ctrl, |
| 456 | INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK, |
| 457 | INFRACFG_AO_PERI_MODULE_DCM_REG0_ON); |
| 458 | |
Weiyi Lu | a4cad36 | 2020-05-13 10:01:14 +0800 | [diff] [blame] | 459 | /* initialize SPM request */ |
| 460 | setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x3ff); |
| 461 | clrsetbits32(&mtk_topckgen->clk_scp_cfg_1, 0x100c, 0x3); |
| 462 | |
| 463 | /* |
| 464 | * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS! |
| 465 | */ |
| 466 | for (i = 0; i < ARRAY_SIZE(mux_sels); i++) |
| 467 | mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); |
| 468 | |
| 469 | /* enable [14] dramc_pll104m_ck */ |
| 470 | setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); |
Weiyi Lu | dac4fa6 | 2020-10-15 14:25:01 +0800 | [diff] [blame] | 471 | |
| 472 | /* reset CONNSYS MCU */ |
| 473 | SET32_BITFIELDS(&mtk_wdt->wdt_swsysrst, |
| 474 | WDT_SWSYSRST_KEY, 0x88, |
| 475 | WDT_SWSYSRST_CONN_MCU, 0x1); |
Weiyi Lu | a4cad36 | 2020-05-13 10:01:14 +0800 | [diff] [blame] | 476 | } |
Weiyi Lu | 86b3bf1 | 2020-06-19 15:28:55 +0800 | [diff] [blame] | 477 | |
| 478 | void mt_pll_raise_little_cpu_freq(u32 freq) |
| 479 | { |
| 480 | /* enable [4] intermediate clock armpll_divider_pll1_ck */ |
| 481 | setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); |
| 482 | |
| 483 | /* switch ca55 clock source to intermediate clock */ |
Rex-BC Chen | 7d9bd17 | 2021-11-11 15:45:27 +0800 | [diff] [blame] | 484 | clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1); |
Weiyi Lu | 86b3bf1 | 2020-06-19 15:28:55 +0800 | [diff] [blame] | 485 | |
| 486 | /* disable armpll_ll frequency output */ |
| 487 | clrbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN); |
| 488 | |
| 489 | /* raise armpll_ll frequency */ |
| 490 | pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq); |
| 491 | |
| 492 | /* enable armpll_ll frequency output */ |
| 493 | setbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN); |
| 494 | udelay(PLL_EN_DELAY); |
| 495 | |
| 496 | /* switch ca55 clock source back to armpll_ll */ |
Rex-BC Chen | 7d9bd17 | 2021-11-11 15:45:27 +0800 | [diff] [blame] | 497 | clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); |
Weiyi Lu | 86b3bf1 | 2020-06-19 15:28:55 +0800 | [diff] [blame] | 498 | |
| 499 | /* disable [4] intermediate clock armpll_divider_pll1_ck */ |
| 500 | clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); |
| 501 | } |
Weiyi Lu | 26d1652 | 2020-06-22 16:21:58 +0800 | [diff] [blame] | 502 | |
| 503 | u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id) |
| 504 | { |
| 505 | u32 output, count, clk_dbg_cfg, clk_misc_cfg_0; |
| 506 | |
| 507 | /* backup */ |
| 508 | clk_dbg_cfg = read32(&mtk_topckgen->clk_dbg_cfg); |
| 509 | clk_misc_cfg_0 = read32(&mtk_topckgen->clk_misc_cfg_0); |
| 510 | |
| 511 | /* set up frequency meter */ |
| 512 | if (type == FMETER_ABIST) { |
| 513 | SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg, |
| 514 | CLK_DBG_CFG_ABIST_CK_SEL, id, |
| 515 | CLK_DBG_CFG_CKGEN_CK_SEL, 0, |
| 516 | CLK_DBG_CFG_METER_CK_SEL, 0); |
| 517 | SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, |
| 518 | CLK_MISC_CFG_0_METER_DIV, 1); |
| 519 | } else if (type == FMETER_CKGEN) { |
| 520 | SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg, |
| 521 | CLK_DBG_CFG_ABIST_CK_SEL, 0, |
| 522 | CLK_DBG_CFG_CKGEN_CK_SEL, id, |
| 523 | CLK_DBG_CFG_METER_CK_SEL, 1); |
| 524 | SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, |
| 525 | CLK_MISC_CFG_0_METER_DIV, 0); |
| 526 | } else { |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 527 | die("unsupported fmeter type\n"); |
Weiyi Lu | 26d1652 | 2020-06-22 16:21:58 +0800 | [diff] [blame] | 528 | } |
| 529 | |
| 530 | /* enable frequency meter */ |
| 531 | write32(&mtk_topckgen->clk26cali_0, 0x1000); |
| 532 | |
| 533 | /* set load count = 1024-1 */ |
| 534 | SET32_BITFIELDS(&mtk_topckgen->clk26cali_1, CLK26CALI_1_LOAD_CNT, 0x3ff); |
| 535 | |
| 536 | /* trigger frequency meter */ |
| 537 | SET32_BITFIELDS(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER, 1); |
| 538 | |
| 539 | /* wait frequency meter until finished */ |
| 540 | if (wait_us(200, !READ32_BITFIELD(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER))) { |
| 541 | count = read32(&mtk_topckgen->clk26cali_1) & 0xffff; |
| 542 | output = (count * 26000) / 1024; /* KHz */ |
| 543 | } else { |
| 544 | printk(BIOS_WARNING, "fmeter timeout\n"); |
| 545 | output = 0; |
| 546 | } |
| 547 | |
| 548 | /* disable frequency meter */ |
| 549 | write32(&mtk_topckgen->clk26cali_0, 0x0000); |
| 550 | |
| 551 | /* restore */ |
| 552 | write32(&mtk_topckgen->clk_dbg_cfg, clk_dbg_cfg); |
| 553 | write32(&mtk_topckgen->clk_misc_cfg_0, clk_misc_cfg_0); |
| 554 | |
| 555 | if (type == FMETER_ABIST) |
| 556 | return output * 2; |
| 557 | else if (type == FMETER_CKGEN) |
| 558 | return output; |
| 559 | |
| 560 | return 0; |
| 561 | } |
Weiyi Lu | 8dfeb06 | 2020-07-23 15:04:48 +0800 | [diff] [blame] | 562 | |
| 563 | void mt_pll_raise_cci_freq(u32 freq) |
| 564 | { |
| 565 | /* enable [4] intermediate clock armpll_divider_pll1_ck */ |
| 566 | setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); |
| 567 | |
| 568 | /* switch cci clock source to intermediate clock */ |
Rex-BC Chen | 7d9bd17 | 2021-11-11 15:45:27 +0800 | [diff] [blame] | 569 | clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1); |
Weiyi Lu | 8dfeb06 | 2020-07-23 15:04:48 +0800 | [diff] [blame] | 570 | |
| 571 | /* disable ccipll frequency output */ |
| 572 | clrbits32(plls[APMIXED_CCIPLL].reg, PLL_EN); |
| 573 | |
| 574 | /* raise ccipll frequency */ |
| 575 | pll_set_rate(&plls[APMIXED_CCIPLL], freq); |
| 576 | |
| 577 | /* enable ccipll frequency output */ |
| 578 | setbits32(plls[APMIXED_CCIPLL].reg, PLL_EN); |
| 579 | udelay(PLL_EN_DELAY); |
| 580 | |
| 581 | /* switch cci clock source back to ccipll */ |
Rex-BC Chen | 7d9bd17 | 2021-11-11 15:45:27 +0800 | [diff] [blame] | 582 | clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); |
Weiyi Lu | 8dfeb06 | 2020-07-23 15:04:48 +0800 | [diff] [blame] | 583 | |
| 584 | /* disable [4] intermediate clock armpll_divider_pll1_ck */ |
| 585 | clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); |
| 586 | } |