Angel Pons | e67ab18 | 2020-04-04 18:51:11 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Hsin-Hsiung Wang | 23b1afe | 2018-10-24 19:18:28 +0800 | [diff] [blame] | 2 | |
Hsin-Hsiung Wang | c10af29 | 2019-03-26 15:38:04 +0800 | [diff] [blame] | 3 | #include <assert.h> |
Elyes HAOUAS | 20eaef0 | 2019-03-29 17:45:28 +0100 | [diff] [blame] | 4 | #include <console/console.h> |
Hsin-Hsiung Wang | 0d0b7a1 | 2019-08-29 15:41:28 +0800 | [diff] [blame] | 5 | #include <delay.h> |
Hsin-Hsiung Wang | 23b1afe | 2018-10-24 19:18:28 +0800 | [diff] [blame] | 6 | #include <soc/pmic_wrap.h> |
| 7 | #include <soc/mt6358.h> |
Tristan Shieh | b75f493 | 2019-04-29 09:12:54 +0800 | [diff] [blame] | 8 | #include <timer.h> |
Hsin-Hsiung Wang | 23b1afe | 2018-10-24 19:18:28 +0800 | [diff] [blame] | 9 | |
| 10 | static struct pmic_setting init_setting[] = { |
| 11 | /* [15:0]: TMA_KEY */ |
| 12 | {0x3A8, 0x9CA7, 0xFFFF, 0}, |
| 13 | /* [1:1]: RG_SRCLKEN_IN0_HW_MODE */ |
| 14 | /* [3:3]: RG_SRCLKEN_IN1_HW_MODE */ |
| 15 | {0x1E, 0xA, 0xA, 0}, |
| 16 | /* [12:8]: RG_MON_GRP_SEL */ |
| 17 | {0x22, 0x1F00, 0x1F00, 0}, |
| 18 | /* [0:0]: RG_SMT_WDTRSTB_IN */ |
| 19 | {0x2E, 0x1, 0x1, 0}, |
| 20 | /* [0:0]: RG_SMT_SPI_CLK */ |
| 21 | {0x30, 0x1, 0x1, 0}, |
| 22 | /* [3:0]: RG_OCTL_SRCLKEN_IN0 */ |
| 23 | /* [7:4]: RG_OCTL_SRCLKEN_IN1 */ |
| 24 | /* [11:8]: RG_OCTL_RTC_32K1V8_0 */ |
| 25 | /* [15:12]: RG_OCTL_RTC_32K1V8_1 */ |
| 26 | {0x36, 0x8888, 0xFFFF, 0}, |
| 27 | /* [3:0]: RG_OCTL_AUD_CLK_MOSI */ |
| 28 | /* [7:4]: RG_OCTL_AUD_DAT_MOSI0 */ |
| 29 | /* [11:8]: RG_OCTL_AUD_DAT_MOSI1 */ |
| 30 | /* [15:12]: RG_OCTL_AUD_SYNC_MOSI */ |
| 31 | {0x3A, 0x8888, 0xFFFF, 0}, |
| 32 | /* [3:0]: RG_OCTL_AUD_CLK_MISO */ |
| 33 | /* [7:4]: RG_OCTL_AUD_DAT_MISO0 */ |
| 34 | /* [11:8]: RG_OCTL_AUD_DAT_MISO1 */ |
| 35 | /* [15:12]: RG_OCTL_AUD_SYNC_MISO */ |
| 36 | {0x3C, 0x8888, 0xFFFF, 0}, |
| 37 | /* [3:0]: RG_OCTL_HOMEKEY */ |
| 38 | /* [7:4]: RG_OCTL_SCP_VREQ_VAO */ |
| 39 | /* [11:8]: RG_OCTL_SD_CARD_DET_N */ |
| 40 | {0x3E, 0x888, 0xFFF, 0}, |
| 41 | /* [15:0]: GPIO_PULLEN0 */ |
| 42 | {0x94, 0x0, 0xFFFF, 0}, |
| 43 | /* [3:3]: RG_INTRP_PRE_OC_CK_PDN */ |
| 44 | /* [4:4]: RG_EFUSE_CK_PDN */ |
| 45 | {0x10C, 0x18, 0x18, 0}, |
| 46 | /* [2:2]: RG_TRIM_128K_CK_PDN */ |
| 47 | {0x112, 0x4, 0x4, 0}, |
| 48 | /* [3:3]: RG_RTC_32K1V8_SEL */ |
| 49 | {0x118, 0x8, 0x8, 0}, |
| 50 | /* [7:7]: RG_PMU_VXO22_ON */ |
| 51 | /* [8:8]: RG_PMU_VXO22_ON_SW_EN */ |
| 52 | {0x12A, 0x100, 0x180, 0}, |
| 53 | /* [4:4]: RG_SRCVOLTEN_LP_EN */ |
| 54 | /* [7:7]: RG_SRCLKEN2_LP_EN */ |
| 55 | /* [11:11]: RG_BUCK_PFM_FLAG_SW_EN */ |
| 56 | /* [13:13]: RG_DCXO26M_RDY_SW_EN */ |
| 57 | {0x134, 0x80, 0x2890, 0}, |
| 58 | /* [5:5]: RG_WDTRSTB_DEB */ |
| 59 | {0x14C, 0x20, 0x20, 0}, |
| 60 | /* [0:0]: RG_INT_MASK_BUCK_TOP */ |
| 61 | /* [1:1]: RG_INT_MASK_LDO_TOP */ |
| 62 | /* [2:2]: RG_INT_MASK_PSC_TOP */ |
| 63 | /* [3:3]: RG_INT_MASK_SCK_TOP */ |
| 64 | /* [4:4]: RG_INT_MASK_BM_TOP */ |
| 65 | /* [5:5]: RG_INT_MASK_HK_TOP */ |
| 66 | /* [6:6]: RG_INT_MASK_XPP_TOP */ |
| 67 | /* [7:7]: RG_INT_MASK_AUD_TOP */ |
| 68 | /* [8:8]: RG_INT_MASK_MISC_TOP */ |
| 69 | {0x198, 0x0, 0x1FF, 0}, |
| 70 | /* [8:7]: XO_AAC_MODE_LPM */ |
| 71 | /* [10:9]: XO_AAC_MODE_FPM */ |
| 72 | {0x790, 0x280, 0x780, 0}, |
| 73 | /* [13:13]: XO_AUDIO_EN_M */ |
| 74 | {0x7AC, 0x0, 0x2000, 0}, |
| 75 | /* [6:6]: RG_RST_DRVSEL */ |
| 76 | {0x98A, 0x40, 0x40, 0}, |
| 77 | /* [0:0]: RG_PWRHOLD */ |
| 78 | {0xA08, 0x1, 0x1, 0}, |
| 79 | /* [8:8]: RG_UVLO_DEC_EN */ |
| 80 | {0xA38, 0x0, 0x100, 0}, |
| 81 | /* [5:5]: RG_STRUP_LONG_PRESS_EXT_CHR_CTRL */ |
| 82 | /* [6:6]: RG_STRUP_LONG_PRESS_EXT_PWRKEY_CTRL */ |
| 83 | /* [7:7]: RG_STRUP_LONG_PRESS_EXT_SPAR_CTRL */ |
| 84 | /* [8:8]: RG_STRUP_LONG_PRESS_EXT_RTCA_CTRL */ |
| 85 | /* [15:15]: RG_STRUP_ENVTEM_CTRL */ |
| 86 | {0xA3C, 0x81E0, 0x81E0, 0}, |
| 87 | /* [0:0]: RG_STRUP_VDRAM2_PG_H2L_EN */ |
| 88 | /* [1:1]: RG_STRUP_VEMC_PG_H2L_EN */ |
| 89 | /* [2:2]: RG_STRUP_VSRAM_PROC12_PG_H2L_EN */ |
| 90 | /* [3:3]: RG_STRUP_VSRAM_PROC11_PG_H2L_EN */ |
| 91 | /* [4:4]: RG_STRUP_VA12_PG_H2L_EN */ |
| 92 | /* [5:5]: RG_STRUP_VSRAM_GPU_PG_H2L_EN */ |
| 93 | /* [6:6]: RG_STRUP_VSRAM_OTHERS_PG_H2L_EN */ |
| 94 | /* [7:7]: RG_STRUP_VAUX18_PG_H2L_EN */ |
| 95 | /* [8:8]: RG_STRUP_VDRAM1_PG_H2L_EN */ |
| 96 | /* [9:9]: RG_STRUP_VPROC12_PG_H2L_EN */ |
| 97 | /* [10:10]: RG_STRUP_VPROC11_PG_H2L_EN */ |
| 98 | /* [11:11]: RG_STRUP_VS1_PG_H2L_EN */ |
| 99 | /* [12:12]: RG_STRUP_VGPU_PG_H2L_EN */ |
| 100 | /* [13:13]: RG_STRUP_VMODEM_PG_H2L_EN */ |
| 101 | /* [14:14]: RG_STRUP_VCORE_PG_H2L_EN */ |
| 102 | /* [15:15]: RG_STRUP_VS2_PG_H2L_EN */ |
| 103 | {0xA44, 0xFFFF, 0xFFFF, 0}, |
| 104 | /* [13:13]: RG_STRUP_RSV_PG_H2L_EN */ |
| 105 | /* [14:14]: RG_STRUP_VAUD28_PG_H2L_EN */ |
| 106 | /* [15:15]: RG_STRUP_VUSB_PG_H2L_EN */ |
| 107 | {0xA46, 0xE000, 0xE000, 0}, |
| 108 | /* [10:10]: RG_SDN_DLY_ENB */ |
| 109 | {0xA62, 0x400, 0x400, 0}, |
| 110 | /* [2:2]: FG_RNG_EN_MODE */ |
| 111 | /* [3:3]: FG_RNG_EN_SW */ |
| 112 | {0xC8A, 0x4, 0xC, 0}, |
| 113 | /* [1:1]: RG_AUXADC_1M_CK_PDN_HWEN */ |
| 114 | /* [3:3]: RG_AUXADC_CK_PDN_HWEN */ |
| 115 | /* [5:5]: RG_AUXADC_RNG_CK_PDN_HWEN */ |
| 116 | /* [7:7]: RG_AUXADC_32K_CK_PDN_HWEN */ |
| 117 | /* [9:9]: RG_AUXADC_1K_CK_PDN_HWEN */ |
| 118 | /* [11:11]: RG_HK_INTRP_CK_PDN_HWEN */ |
| 119 | {0xF8C, 0xAAA, 0xAAA, 0}, |
| 120 | /* [15:15]: AUXADC_CK_AON */ |
| 121 | {0x1188, 0x0, 0x8000, 0}, |
| 122 | /* [14:12]: AUXADC_AVG_NUM_CH0 */ |
| 123 | {0x119E, 0x6000, 0x7000, 0}, |
| 124 | /* [13:12]: AUXADC_TRIM_CH6_SEL */ |
| 125 | {0x11A2, 0x0, 0x3000, 0}, |
| 126 | /* [14:14]: AUXADC_START_SHADE_EN */ |
| 127 | {0x11B0, 0x4000, 0x4000, 0}, |
| 128 | /* [8:8]: AUXADC_DATA_REUSE_EN */ |
| 129 | {0x11B4, 0x0, 0x100, 0}, |
| 130 | /* [9:0]: AUXADC_MDRT_DET_PRD */ |
| 131 | /* [15:15]: AUXADC_MDRT_DET_EN */ |
| 132 | {0x123A, 0x8040, 0x83FF, 0}, |
| 133 | /* [2:2]: AUXADC_MDRT_DET_WKUP_EN */ |
| 134 | {0x123E, 0x4, 0x4, 0}, |
| 135 | /* [0:0]: AUXADC_MDRT_DET_START_SEL */ |
| 136 | {0x1242, 0x1, 0x1, 0}, |
| 137 | /* [2:2]: AUXADC_LBAT_CK_SW_MODE */ |
| 138 | /* [4:4]: AUXADC_BAT_TEMP_CK_SW_MODE */ |
| 139 | /* [6:6]: AUXADC_LBAT2_CK_SW_MODE */ |
| 140 | /* [8:8]: AUXADC_NAG_CK_SW_MODE */ |
| 141 | {0x1260, 0x0, 0x154, 0}, |
| 142 | /* [3:3]: RG_BUCK_DCM_MODE */ |
| 143 | {0x1312, 0x8, 0x8, 0}, |
| 144 | /* [8:8]: RG_BUCK_K_CK_EN */ |
| 145 | {0x1334, 0x0, 0x100, 0}, |
| 146 | /* [8:8]: RG_BUCK_VPA_OC_SDN_EN */ |
| 147 | {0x1346, 0x100, 0x100, 0}, |
| 148 | /* [6:0]: RG_BUCK_VPROC11_VOSEL_SLEEP */ |
| 149 | {0x138A, 0x10, 0x7F, 0}, |
| 150 | /* [6:0]: RG_BUCK_VPROC11_SFCHG_FRATE */ |
| 151 | {0x138C, 0x15, 0x7F, 0}, |
| 152 | /* [5:4]: RG_BUCK_VPROC11_DVS_EN_CTRL */ |
| 153 | /* [13:12]: RG_BUCK_VPROC11_DVS_DOWN_CTRL */ |
| 154 | {0x138E, 0x1030, 0x3030, 0}, |
| 155 | /* [6:0]: RG_BUCK_VPROC12_VOSEL_SLEEP */ |
| 156 | {0x140A, 0x10, 0x7F, 0}, |
| 157 | /* [6:0]: RG_BUCK_VPROC12_SFCHG_FRATE */ |
| 158 | {0x140C, 0x15, 0x7F, 0}, |
| 159 | /* [5:4]: RG_BUCK_VPROC12_DVS_EN_CTRL */ |
| 160 | /* [13:12]: RG_BUCK_VPROC12_DVS_DOWN_CTRL */ |
| 161 | {0x140E, 0x1030, 0x3030, 0}, |
| 162 | /* [6:0]: RG_BUCK_VCORE_VOSEL_SLEEP */ |
| 163 | {0x148A, 0x10, 0x7F, 0}, |
| 164 | /* [5:4]: RG_BUCK_VCORE_DVS_EN_CTRL */ |
| 165 | /* [13:12]: RG_BUCK_VCORE_DVS_DOWN_CTRL */ |
| 166 | {0x148E, 0x1030, 0x3030, 0}, |
| 167 | /* [5:5]: RG_BUCK_VCORE_OSC_SEL_DIS */ |
| 168 | {0x14A2, 0x20, 0x20, 0}, |
| 169 | /* [6:0]: RG_BUCK_VGPU_VOSEL_SLEEP */ |
| 170 | {0x150A, 0x10, 0x7F, 0}, |
| 171 | /* [5:4]: RG_BUCK_VGPU_DVS_EN_CTRL */ |
| 172 | /* [13:12]: RG_BUCK_VGPU_DVS_DOWN_CTRL */ |
| 173 | {0x150E, 0x1030, 0x3030, 0}, |
| 174 | /* [6:0]: RG_BUCK_VMODEM_VOSEL_SLEEP */ |
| 175 | {0x158A, 0x8, 0x7F, 0}, |
| 176 | /* [6:0]: RG_BUCK_VMODEM_SFCHG_FRATE */ |
| 177 | /* [14:8]: RG_BUCK_VMODEM_SFCHG_RRATE */ |
| 178 | {0x158C, 0x90C, 0x7F7F, 0}, |
| 179 | /* [5:4]: RG_BUCK_VMODEM_DVS_EN_CTRL */ |
| 180 | /* [13:12]: RG_BUCK_VMODEM_DVS_DOWN_CTRL */ |
| 181 | {0x158E, 0x1030, 0x3030, 0}, |
| 182 | /* [3:2]: RG_BUCK_VMODEM_OC_WND */ |
| 183 | {0x159C, 0x8, 0xC, 0}, |
| 184 | /* [5:5]: RG_BUCK_VMODEM_OSC_SEL_DIS */ |
| 185 | {0x15A2, 0x20, 0x20, 0}, |
| 186 | /* [6:0]: RG_BUCK_VS1_VOSEL_SLEEP */ |
| 187 | {0x168A, 0x50, 0x7F, 0}, |
| 188 | /* [6:0]: RG_BUCK_VS1_SFCHG_FRATE */ |
| 189 | /* [14:8]: RG_BUCK_VS1_SFCHG_RRATE */ |
| 190 | {0x168C, 0x1964, 0x7F7F, 0}, |
| 191 | /* [5:4]: RG_BUCK_VS1_DVS_EN_CTRL */ |
| 192 | /* [13:12]: RG_BUCK_VS1_DVS_DOWN_CTRL */ |
| 193 | {0x168E, 0x2020, 0x3030, 0}, |
| 194 | /* [5:5]: RG_BUCK_VS1_OSC_SEL_DIS */ |
| 195 | {0x16A2, 0x20, 0x20, 0}, |
| 196 | /* [6:0]: RG_BUCK_VS1_VOTER_VOSEL */ |
| 197 | {0x16AA, 0x48, 0x7F, 0}, |
| 198 | /* [6:0]: RG_BUCK_VS2_SFCHG_FRATE */ |
| 199 | /* [14:8]: RG_BUCK_VS2_SFCHG_RRATE */ |
| 200 | {0x170C, 0x1964, 0x7F7F, 0}, |
| 201 | /* [5:4]: RG_BUCK_VS2_DVS_EN_CTRL */ |
| 202 | /* [13:12]: RG_BUCK_VS2_DVS_DOWN_CTRL */ |
| 203 | {0x170E, 0x2020, 0x3030, 0}, |
| 204 | /* [6:0]: RG_BUCK_VS2_VOTER_VOSEL */ |
| 205 | {0x172A, 0x3C, 0x7F, 0}, |
| 206 | /* [6:0]: RG_BUCK_VPA_SFCHG_FRATE */ |
| 207 | /* [14:8]: RG_BUCK_VPA_SFCHG_RRATE */ |
| 208 | {0x178C, 0x202, 0x7F7F, 0}, |
| 209 | /* [1:0]: RG_BUCK_VPA_DVS_TRANST_TD */ |
| 210 | /* [5:4]: RG_BUCK_VPA_DVS_TRANST_CTRL */ |
| 211 | /* [6:6]: RG_BUCK_VPA_DVS_TRANST_ONCE */ |
| 212 | {0x178E, 0x70, 0x73, 0}, |
| 213 | /* [3:2]: RG_BUCK_VPA_OC_WND */ |
| 214 | {0x1790, 0xC, 0xC, 0}, |
| 215 | /* [5:0]: RG_BUCK_VPA_VOSEL_DLC011 */ |
| 216 | /* [13:8]: RG_BUCK_VPA_VOSEL_DLC111 */ |
| 217 | {0x1798, 0x2810, 0x3F3F, 0}, |
| 218 | /* [13:8]: RG_BUCK_VPA_VOSEL_DLC001 */ |
| 219 | {0x179A, 0x800, 0x3F00, 0}, |
| 220 | /* [0:0]: RG_BUCK_VPA_MSFG_EN */ |
| 221 | {0x179E, 0x1, 0x1, 0}, |
| 222 | /* [13:12]: RG_VPA_BURSTH */ |
| 223 | {0x1808, 0x2000, 0x3000, 0}, |
| 224 | /* [5:5]: RG_VPROC11_FCOT */ |
| 225 | /* [6:6]: RG_VPROC12_FCOT */ |
| 226 | {0x180C, 0x60, 0x60, 0}, |
| 227 | /* [1:0]: RG_VPROC11_TB_WIDTH */ |
| 228 | /* [3:2]: RG_VPROC12_TB_WIDTH */ |
| 229 | /* [5:4]: RG_VPROC11_UG_SR */ |
| 230 | /* [7:6]: RG_VPROC11_LG_SR */ |
| 231 | /* [9:8]: RG_VPROC12_UG_SR */ |
| 232 | /* [11:10]: RG_VPROC12_LG_SR */ |
| 233 | /* [14:12]: RG_VPROC11_PFM_TON */ |
| 234 | {0x1814, 0x3FF0, 0x7FFF, 0}, |
| 235 | /* [2:0]: RG_VPROC12_PFM_TON */ |
| 236 | {0x1816, 0x3, 0x7, 0}, |
| 237 | /* [5:0]: RG_VPROC11_TRAN_BST */ |
| 238 | /* [12:7]: RG_VPROC12_TRAN_BST */ |
| 239 | /* [15:13]: RG_VPROC11_COTRAMP_SLP */ |
| 240 | {0x181A, 0x6081, 0xFFBF, 0}, |
| 241 | /* [2:0]: RG_VPROC12_COTRAMP_SLP */ |
| 242 | /* [8:7]: RG_VPROC11_VREFTB */ |
| 243 | /* [10:9]: RG_VPROC12_VREFTB */ |
| 244 | {0x181C, 0x503, 0x787, 0}, |
| 245 | /* [15:0]: RG_VPROC11_RSV */ |
| 246 | {0x181E, 0xA662, 0xFFFF, 0}, |
| 247 | /* [15:0]: RG_VPROC12_RSV */ |
| 248 | {0x1820, 0xA662, 0xFFFF, 0}, |
| 249 | /* [2:0]: RG_VPROC11_CSP */ |
| 250 | /* [5:3]: RG_VPROC11_CSN */ |
| 251 | /* [8:6]: RG_VPROC12_CSP */ |
| 252 | /* [11:9]: RG_VPROC12_CSN */ |
| 253 | {0x1824, 0xDB6, 0xFFF, 0}, |
| 254 | /* [5:5]: RG_VCORE_FCOT */ |
| 255 | /* [6:6]: RG_VGPU_FCOT */ |
| 256 | /* [8:8]: RG_VCORE_TBDIS */ |
| 257 | {0x1828, 0x160, 0x160, 0}, |
| 258 | /* [1:0]: RG_VCORE_TB_WIDTH */ |
| 259 | /* [3:2]: RG_VGPU_TB_WIDTH */ |
| 260 | /* [5:4]: RG_VCORE_UG_SR */ |
| 261 | /* [7:6]: RG_VCORE_LG_SR */ |
| 262 | /* [9:8]: RG_VGPU_UG_SR */ |
| 263 | /* [11:10]: RG_VGPU_LG_SR */ |
| 264 | /* [14:12]: RG_VCORE_PFM_TON */ |
| 265 | {0x1830, 0x3FF0, 0x7FFF, 0}, |
| 266 | /* [2:0]: RG_VGPU_PFM_TON */ |
| 267 | {0x1832, 0x3, 0x7, 0}, |
| 268 | /* [5:0]: RG_VCORE_TRAN_BST */ |
| 269 | /* [12:7]: RG_VGPU_TRAN_BST */ |
| 270 | /* [15:13]: RG_VCORE_COTRAMP_SLP */ |
| 271 | {0x1836, 0x6081, 0xFFBF, 0}, |
| 272 | /* [2:0]: RG_VGPU_COTRAMP_SLP */ |
| 273 | /* [8:7]: RG_VCORE_VREFTB */ |
| 274 | /* [10:9]: RG_VGPU_VREFTB */ |
| 275 | {0x1838, 0x503, 0x787, 0}, |
| 276 | /* [15:0]: RG_VCORE_RSV */ |
| 277 | {0x183A, 0xA262, 0xFFFF, 0}, |
| 278 | /* [15:0]: RG_VGPU_RSV */ |
| 279 | {0x183C, 0xA262, 0xFFFF, 0}, |
| 280 | /* [11:0]: RG_VCORE_CSP */ |
| 281 | /* [5:3]: RG_VCORE_CSN */ |
| 282 | /* [8:6]: RG_VGPU_CSP */ |
| 283 | /* [11:9]: RG_VGPU_CSN */ |
| 284 | {0x1840, 0xDB6, 0xFFF, 0}, |
| 285 | /* [2:0]: RG_VPROC11_RPSI1_TRIM */ |
| 286 | {0x1854, 0x0, 0x7, 0}, |
| 287 | /* [12:10]: RG_VPROC12_RPSI1_TRIM */ |
| 288 | {0x1856, 0x0, 0x1C00, 0}, |
| 289 | /* [2:0]: RG_VCORE_RPSI1_TRIM */ |
| 290 | {0x185C, 0x0, 0x7, 0}, |
| 291 | /* [12:10]: RG_VGPU_RPSI1_TRIM */ |
| 292 | {0x185E, 0x0, 0x1C00, 0}, |
| 293 | /* [5:2]: RG_VMODEM_RCOMP */ |
| 294 | /* [6:6]: RG_VMODEM_TB_DIS */ |
| 295 | /* [11:9]: RG_VMODEM_PFM_TON */ |
| 296 | {0x1888, 0x420, 0xE7C, 0}, |
| 297 | /* [2:0]: RG_VMODEM_COTRAMP_SLP */ |
| 298 | /* [11:10]: RG_VMODEM_VREFUP */ |
| 299 | /* [13:12]: RG_VMODEM_TB_WIDTH */ |
| 300 | {0x188A, 0x801, 0x3C07, 0}, |
| 301 | /* [1:0]: RG_VMODEM_UG_SR */ |
| 302 | /* [3:2]: RG_VMODEM_LG_SR */ |
| 303 | /* [5:4]: RG_VMODEM_CCOMP */ |
| 304 | {0x188C, 0x1F, 0x3F, 0}, |
| 305 | /* [15:0]: RG_VMODEM_RSV */ |
| 306 | {0x188E, 0x129A, 0xFFFF, 0}, |
| 307 | /* [5:3]: RG_VMODEM_CSN */ |
| 308 | /* [8:6]: RG_VMODEM_SONIC_PFM_TON */ |
| 309 | {0x1894, 0x58, 0x1F8, 0}, |
| 310 | /* [5:2]: RG_VDRAM1_RCOMP */ |
| 311 | /* [6:6]: RG_VDRAM1_TB_DIS */ |
| 312 | {0x1896, 0x1C, 0x7C, 0}, |
| 313 | /* [2:0]: RG_VDRAM1_COTRAMP_SLP */ |
| 314 | /* [11:10]: RG_VDRAM1_VREFUP */ |
| 315 | /* [13:12]: RG_VDRAM1_TB_WIDTH */ |
| 316 | {0x1898, 0x1805, 0x3C07, 0}, |
| 317 | /* [3:0]: RG_VDRAM1_UG_SR */ |
| 318 | {0x189A, 0xF, 0xF, 0}, |
| 319 | /* [15:0]: RG_VDRAM1_RSV */ |
| 320 | {0x189C, 0x221A, 0xFFFF, 0}, |
| 321 | /* [2:0]: RG_VDRAM1_CSP */ |
| 322 | /* [5:3]: RG_VDRAM1_CSN */ |
| 323 | {0x18A0, 0x2E, 0x3F, 0}, |
| 324 | /* [6:6]: RG_VS1_TB_DIS */ |
| 325 | {0x18A2, 0x0, 0x40, 0}, |
| 326 | /* [2:0]: RG_VS1_COTRAMP_SLP */ |
| 327 | /* [11:10]: RG_VS1_VREFUP */ |
| 328 | /* [13:12]: RG_VS1_TB_WIDTH */ |
| 329 | {0x18A4, 0x2C06, 0x3C07, 0}, |
| 330 | /* [1:0]: RG_VS1_UG_SR */ |
| 331 | /* [3:2]: RG_VS1_LG_SR */ |
| 332 | {0x18A6, 0xF, 0xF, 0}, |
| 333 | /* [15:0]: RG_VS1_RSV */ |
| 334 | {0x18A8, 0x221A, 0xFFFF, 0}, |
| 335 | /* [2:0]: RG_VS1_CSP */ |
| 336 | /* [5:3]: RG_VS1_CSN */ |
| 337 | {0x18AC, 0x2E, 0x3F, 0}, |
| 338 | /* [6:6]: RG_VS2_TB_DIS */ |
| 339 | {0x18AE, 0x0, 0x40, 0}, |
| 340 | /* [2:0]: RG_VS2_COTRAMP_SLP */ |
| 341 | /* [11:10]: RG_VS2_VREFUP */ |
| 342 | /* [13:12]: RG_VS2_TB_WIDTH */ |
| 343 | {0x18B0, 0x1805, 0x3C07, 0}, |
| 344 | /* [1:0]: RG_VS2_UG_SR */ |
| 345 | /* [3:2]: RG_VS2_LG_SR */ |
| 346 | {0x18B2, 0xF, 0xF, 0}, |
| 347 | /* [15:0]: RG_VS2_RSV */ |
| 348 | {0x18B4, 0x221A, 0xFFFF, 0}, |
| 349 | /* [2:0]: RG_VS2_CSP */ |
| 350 | /* [5:3]: RG_VS2_CSN */ |
| 351 | {0x18B8, 0x2E, 0x3F, 0}, |
| 352 | /* [5:4]: RG_VPA_CSMIR */ |
| 353 | /* [7:6]: RG_VPA_CSL */ |
| 354 | /* [10:10]: RG_VPA_AZC_EN */ |
| 355 | {0x18BC, 0x50, 0x4F0, 0}, |
| 356 | /* [3:2]: RG_VPA_SLEW */ |
| 357 | /* [5:4]: RG_VPA_SLEW_NMOS */ |
| 358 | /* [7:6]: RG_VPA_MIN_ON */ |
| 359 | {0x18BE, 0x3C, 0xFC, 0}, |
| 360 | /* [9:8]: RG_VPA_MIN_PK */ |
| 361 | {0x18C0, 0x0, 0x300, 0}, |
| 362 | /* [7:0]: RG_VPA_RSV1 */ |
| 363 | /* [15:8]: RG_VPA_RSV2 */ |
| 364 | {0x18C2, 0x8886, 0xFFFF, 0}, |
| 365 | /* [11:8]: RG_VPA_NLIM_SEL */ |
| 366 | {0x18D8, 0x700, 0xF00, 0}, |
| 367 | /* [0:0]: RG_LDO_32K_CK_PDN_HWEN */ |
| 368 | /* [1:1]: RG_LDO_INTRP_CK_PDN_HWEN */ |
| 369 | {0x1A0E, 0x3, 0x3, 0}, |
| 370 | /* [0:0]: RG_LDO_DCM_MODE */ |
| 371 | {0x1A10, 0x1, 0x1, 0}, |
| 372 | /* [0:0]: RG_LDO_VFE28_CK_SW_MODE */ |
| 373 | {0x1A12, 0x0, 0x1, 0}, |
| 374 | /* [0:0]: RG_LDO_VXO22_CK_SW_MODE */ |
| 375 | {0x1A14, 0x0, 0x1, 0}, |
| 376 | /* [0:0]: RG_LDO_VRF18_CK_SW_MODE */ |
| 377 | {0x1A16, 0x0, 0x1, 0}, |
| 378 | /* [0:0]: RG_LDO_VRF12_CK_SW_MODE */ |
| 379 | {0x1A18, 0x0, 0x1, 0}, |
| 380 | /* [0:0]: RG_LDO_VEFUSE_CK_SW_MODE */ |
| 381 | {0x1A1A, 0x0, 0x1, 0}, |
| 382 | /* [0:0]: RG_LDO_VCN33_CK_SW_MODE */ |
| 383 | {0x1A1C, 0x0, 0x1, 0}, |
| 384 | /* [0:0]: RG_LDO_VCN28_CK_SW_MODE */ |
| 385 | {0x1A1E, 0x0, 0x1, 0}, |
| 386 | /* [0:0]: RG_LDO_VCN18_CK_SW_MODE */ |
| 387 | {0x1A20, 0x0, 0x1, 0}, |
| 388 | /* [0:0]: RG_LDO_VCAMA1_CK_SW_MODE */ |
| 389 | {0x1A22, 0x0, 0x1, 0}, |
| 390 | /* [0:0]: RG_LDO_VCAMA2_CK_SW_MODE */ |
| 391 | {0x1A24, 0x0, 0x1, 0}, |
| 392 | /* [0:0]: RG_LDO_VCAMD_CK_SW_MODE */ |
| 393 | {0x1A26, 0x0, 0x1, 0}, |
| 394 | /* [0:0]: RG_LDO_VCAMIO_CK_SW_MODE */ |
| 395 | {0x1A28, 0x0, 0x1, 0}, |
| 396 | /* [0:0]: RG_LDO_VLDO28_CK_SW_MODE */ |
| 397 | {0x1A2A, 0x0, 0x1, 0}, |
| 398 | /* [0:0]: RG_LDO_VA12_CK_SW_MODE */ |
| 399 | {0x1A2C, 0x0, 0x1, 0}, |
| 400 | /* [0:0]: RG_LDO_VAUX18_CK_SW_MODE */ |
| 401 | {0x1A2E, 0x0, 0x1, 0}, |
| 402 | /* [0:0]: RG_LDO_VAUD28_CK_SW_MODE */ |
| 403 | {0x1A30, 0x0, 0x1, 0}, |
| 404 | /* [0:0]: RG_LDO_VIO28_CK_SW_MODE */ |
| 405 | {0x1A32, 0x0, 0x1, 0}, |
| 406 | /* [0:0]: RG_LDO_VIO18_CK_SW_MODE */ |
| 407 | {0x1A34, 0x0, 0x1, 0}, |
| 408 | /* [0:0]: RG_LDO_VSRAM_PROC11_CK_SW_MODE */ |
| 409 | {0x1A36, 0x0, 0x1, 0}, |
| 410 | /* [0:0]: RG_LDO_VSRAM_PROC12_CK_SW_MODE */ |
| 411 | {0x1A38, 0x0, 0x1, 0}, |
| 412 | /* [0:0]: RG_LDO_VSRAM_OTHERS_CK_SW_MODE */ |
| 413 | {0x1A3A, 0x0, 0x1, 0}, |
| 414 | /* [0:0]: RG_LDO_VSRAM_GPU_CK_SW_MODE */ |
| 415 | {0x1A3C, 0x0, 0x1, 0}, |
| 416 | /* [0:0]: RG_LDO_VDRAM2_CK_SW_MODE */ |
| 417 | {0x1A3E, 0x0, 0x1, 0}, |
| 418 | /* [0:0]: RG_LDO_VMC_CK_SW_MODE */ |
| 419 | {0x1A40, 0x0, 0x1, 0}, |
| 420 | /* [0:0]: RG_LDO_VMCH_CK_SW_MODE */ |
| 421 | {0x1A42, 0x0, 0x1, 0}, |
| 422 | /* [0:0]: RG_LDO_VEMC_CK_SW_MODE */ |
| 423 | {0x1A44, 0x0, 0x1, 0}, |
| 424 | /* [0:0]: RG_LDO_VSIM1_CK_SW_MODE */ |
| 425 | {0x1A46, 0x0, 0x1, 0}, |
| 426 | /* [0:0]: RG_LDO_VSIM2_CK_SW_MODE */ |
| 427 | {0x1A48, 0x0, 0x1, 0}, |
| 428 | /* [0:0]: RG_LDO_VIBR_CK_SW_MODE */ |
| 429 | {0x1A4A, 0x0, 0x1, 0}, |
| 430 | /* [0:0]: RG_LDO_VUSB_CK_SW_MODE */ |
| 431 | {0x1A4C, 0x0, 0x1, 0}, |
| 432 | /* [0:0]: RG_LDO_VBIF28_CK_SW_MODE */ |
| 433 | {0x1A4E, 0x0, 0x1, 0}, |
| 434 | /* [6:0]: RG_LDO_VSRAM_PROC11_VOSEL_SLEEP */ |
| 435 | {0x1B48, 0x10, 0x7F, 0}, |
| 436 | /* [6:0]: RG_LDO_VSRAM_PROC11_SFCHG_FRATE */ |
| 437 | /* [14:8]: RG_LDO_VSRAM_PROC11_SFCHG_RRATE */ |
| 438 | {0x1B4A, 0xF15, 0x7F7F, 0}, |
| 439 | /* [6:0]: RG_LDO_VSRAM_PROC12_VOSEL_SLEEP */ |
| 440 | {0x1B8A, 0x10, 0x7F, 0}, |
| 441 | /* [6:0]: RG_LDO_VSRAM_PROC12_SFCHG_FRATE */ |
| 442 | /* [14:8]: RG_LDO_VSRAM_PROC12_SFCHG_RRATE */ |
| 443 | {0x1B8C, 0xF15, 0x7F7F, 0}, |
| 444 | /* [6:0]: RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP */ |
| 445 | {0x1BA8, 0x38, 0x7F, 0}, |
| 446 | /* [6:0]: RG_LDO_VSRAM_OTHERS_SFCHG_FRATE */ |
| 447 | /* [14:8]: RG_LDO_VSRAM_OTHERS_SFCHG_RRATE */ |
| 448 | {0x1BAA, 0x70F, 0x7F7F, 0}, |
| 449 | /* [1:0]: RG_LDO_VSRAM_OTHERS_DVS_TRANS_TD */ |
| 450 | {0x1BAC, 0x0, 0x3, 0}, |
| 451 | /* [6:0]: RG_LDO_VSRAM_GPU_VOSEL_SLEEP */ |
| 452 | {0x1BCA, 0x10, 0x7F, 0}, |
| 453 | /* [6:0]: RG_LDO_VSRAM_GPU_SFCHG_FRATE */ |
| 454 | /* [14:8]: RG_LDO_VSRAM_GPU_SFCHG_RRATE */ |
| 455 | {0x1BCC, 0x70F, 0x7F7F, 0}, |
| 456 | /* [4:0]: RG_VSRAM_PROC11_RSV_H */ |
| 457 | {0x1EA2, 0x1B, 0x1F, 0}, |
| 458 | /* [12:10]: RG_VSRAM_PROC12_RSV_H */ |
| 459 | {0x1EA4, 0xC00, 0x1C00, 0}, |
| 460 | /* [12:10]: RG_VSRAM_OTHERS_RSV_H */ |
| 461 | {0x1EA6, 0xC00, 0x1C00, 0}, |
| 462 | /* [12:10]: RG_VSRAM_GPU_RSV_H */ |
| 463 | {0x1EA8, 0xC00, 0x1C00, 0}, |
| 464 | /* [15:0]: TMA_KEY */ |
| 465 | {0x3A8, 0x0, 0xFFFF, 0}, |
| 466 | |
| 467 | /* MT6358 HW tracking init */ |
| 468 | /* [6:0]: RG_LDO_VSRAM_PROC11_VOSEL_DELTA */ |
| 469 | /* [14:8]: RG_LDO_VSRAM_PROC11_VOSEL_OFFSET */ |
| 470 | {0x1B66, 0x1000, 0x7F7F, 0}, |
| 471 | /* [6:0]: RG_LDO_VSRAM_PROC11_VOSEL_ON_LB */ |
| 472 | /* [14:8]: RG_LDO_VSRAM_PROC11_VOSEL_ON_HB */ |
| 473 | {0x1B68, 0x6340, 0x7F7F, 0}, |
| 474 | /* [1:1]: RG_LDO_VSRAM_PROC11_TRACK_ON_CTRL */ |
| 475 | /* [2:2]: RG_LDO_VSRAM_PROC11_TRACK_VPROC11_ON_CTRL */ |
| 476 | {0x1B64, 0x6, 0x6, 0}, |
| 477 | /* [6:0]: RG_LDO_VSRAM_PROC12_VOSEL_DELTA */ |
| 478 | /* [14:8]: RG_LDO_VSRAM_PROC12_VOSEL_OFFSET */ |
| 479 | {0x1B6E, 0x1000, 0x7F7F, 0}, |
| 480 | /* [6:0]: RG_LDO_VSRAM_PROC12_VOSEL_ON_LB */ |
| 481 | /* [14:8]: RG_LDO_VSRAM_PROC12_VOSEL_ON_HB */ |
| 482 | {0x1B70, 0x6340, 0x7F7F, 0}, |
| 483 | /* [2:1]: RG_LDO_VSRAM_PROC12_TRACK_ON_CTRL */ |
| 484 | /* [2:2]: RG_LDO_VSRAM_PROC12_TRACK_VPROC12_ON_CTRL */ |
| 485 | {0x1B6C, 0x6, 0x6, 0}, |
Tristan Shieh | dcb2eef | 2019-04-23 14:09:52 +0800 | [diff] [blame] | 486 | |
| 487 | /* Vproc11/Vproc12 to 1.05V */ |
Hsin-Hsiung Wang | fd54acf | 2019-06-03 15:38:53 +0800 | [diff] [blame] | 488 | /* [6:0]: RG_BUCK_VPROC11_VOSEL */ |
Tristan Shieh | dcb2eef | 2019-04-23 14:09:52 +0800 | [diff] [blame] | 489 | {0x13a6, 0x58, 0x7F, 0}, |
Hsin-Hsiung Wang | fd54acf | 2019-06-03 15:38:53 +0800 | [diff] [blame] | 490 | /* [6:0]: RG_BUCK_VPROC12_VOSEL */ |
| 491 | {0x1426, 0x58, 0x7F, 0}, |
Hsin-Hsiung Wang | 23b1afe | 2018-10-24 19:18:28 +0800 | [diff] [blame] | 492 | }; |
| 493 | |
| 494 | static struct pmic_setting lp_setting[] = { |
| 495 | /* Suspend */ |
| 496 | /* [0:0]: RG_BUCK_VPROC11_SW_OP_EN */ |
| 497 | {0x1390, 0x1, 0x1, 0}, |
| 498 | /* [0:0]: RG_BUCK_VCORE_SW_OP_EN */ |
| 499 | {0x1490, 0x1, 0x1, 0}, |
| 500 | /* [0:0]: RG_BUCK_VGPU_SW_OP_EN */ |
| 501 | {0x1510, 0x1, 0x1, 0}, |
| 502 | /* [0:0]: RG_BUCK_VMODEM_SW_OP_EN */ |
| 503 | {0x1590, 0x1, 0x1, 0}, |
| 504 | /* [0:0]: RG_BUCK_VS1_SW_OP_EN */ |
| 505 | {0x1690, 0x1, 0x1, 0}, |
| 506 | /* [1:1]: RG_BUCK_VS2_HW0_OP_EN */ |
| 507 | {0x1710, 0x1, 0x1, 1}, |
| 508 | /* [1:1]: RG_BUCK_VS2_HW0_OP_CFG */ |
| 509 | {0x1716, 0x1, 0x1, 1}, |
| 510 | /* [1:1]: RG_BUCK_VDRAM1_HW0_OP_EN */ |
| 511 | {0x1610, 0x1, 0x1, 1}, |
| 512 | /* [1:1]: RG_BUCK_VDRAM1_HW0_OP_CFG */ |
| 513 | {0x1616, 0x1, 0x1, 1}, |
| 514 | /* [0:0]: RG_BUCK_VPROC12_SW_OP_EN */ |
| 515 | {0x1410, 0x1, 0x1, 0}, |
| 516 | /* [0:0]: RG_LDO_VSRAM_GPU_SW_OP_EN */ |
| 517 | {0x1BD0, 0x1, 0x1, 0}, |
| 518 | /* [1:1]: RG_LDO_VSRAM_OTHERS_HW0_OP_EN */ |
| 519 | {0x1BAE, 0x1, 0x1, 1}, |
| 520 | /* [1:1]: RG_LDO_VSRAM_OTHERS_HW0_OP_CFG */ |
| 521 | {0x1BB4, 0x1, 0x1, 1}, |
| 522 | /* [0:0]: RG_LDO_VSRAM_PROC11_SW_OP_EN */ |
| 523 | {0x1B4E, 0x1, 0x1, 0}, |
| 524 | /* [1:1]: RG_LDO_VXO22_HW0_OP_EN */ |
| 525 | {0x1A8A, 0x1, 0x1, 1}, |
| 526 | /* [1:1]: RG_LDO_VXO22_HW0_OP_CFG */ |
| 527 | {0x1A90, 0x1, 0x1, 1}, |
| 528 | /* [2:2]: RG_LDO_VRF18_HW1_OP_EN */ |
| 529 | {0x1C1E, 0x1, 0x1, 2}, |
| 530 | /* [2:2]: RG_LDO_VRF18_HW1_OP_CFG */ |
| 531 | {0x1C24, 0x0, 0x1, 2}, |
| 532 | /* [2:2]: RG_LDO_VRF12_HW1_OP_EN */ |
| 533 | {0x1C32, 0x1, 0x1, 2}, |
| 534 | /* [2:2]: RG_LDO_VRF12_HW1_OP_CFG */ |
| 535 | {0x1C38, 0x0, 0x1, 2}, |
| 536 | /* [0:0]: RG_LDO_VEFUSE_SW_OP_EN */ |
| 537 | {0x1C46, 0x1, 0x1, 0}, |
| 538 | /* [0:0]: RG_LDO_VCN33_SW_OP_EN */ |
| 539 | {0x1D1E, 0x1, 0x1, 0}, |
| 540 | /* [0:0]: RG_LDO_VCN33_SW_OP_EN */ |
| 541 | {0x1D1E, 0x1, 0x1, 0}, |
| 542 | /* [0:0]: RG_LDO_VCN28_SW_OP_EN */ |
| 543 | {0x1D8A, 0x1, 0x1, 0}, |
| 544 | /* [0:0]: RG_LDO_VCN18_SW_OP_EN */ |
| 545 | {0x1C5A, 0x1, 0x1, 0}, |
| 546 | /* [0:0]: RG_LDO_VCAMA1_SW_OP_EN */ |
| 547 | {0x1C6E, 0x1, 0x1, 0}, |
| 548 | /* [0:0]: RG_LDO_VCAMD_SW_OP_EN */ |
| 549 | {0x1C9E, 0x1, 0x1, 0}, |
| 550 | /* [0:0]: RG_LDO_VCAMA2_SW_OP_EN */ |
| 551 | {0x1C8A, 0x1, 0x1, 0}, |
| 552 | /* [0:0]: RG_LDO_VSRAM_PROC12_SW_OP_EN */ |
| 553 | {0x1B90, 0x1, 0x1, 0}, |
| 554 | /* [0:0]: RG_LDO_VCAMIO_SW_OP_EN */ |
| 555 | {0x1CB2, 0x1, 0x1, 0}, |
| 556 | /* [0:0]: RG_LDO_VLDO28_SW_OP_EN */ |
| 557 | {0x1D34, 0x1, 0x1, 0}, |
| 558 | /* [0:0]: RG_LDO_VLDO28_SW_OP_EN */ |
| 559 | {0x1D34, 0x1, 0x1, 0}, |
| 560 | /* [1:1]: RG_LDO_VA12_HW0_OP_EN */ |
| 561 | {0x1A9E, 0x1, 0x1, 1}, |
| 562 | /* [1:1]: RG_LDO_VA12_HW0_OP_CFG */ |
| 563 | {0x1AA4, 0x1, 0x1, 1}, |
| 564 | /* [1:1]: RG_LDO_VAUX18_HW0_OP_EN */ |
| 565 | {0x1AB2, 0x1, 0x1, 1}, |
| 566 | /* [1:1]: RG_LDO_VAUX18_HW0_OP_CFG */ |
| 567 | {0x1AB8, 0x1, 0x1, 1}, |
| 568 | /* [1:1]: RG_LDO_VAUD28_HW0_OP_EN */ |
| 569 | {0x1AC6, 0x1, 0x1, 1}, |
| 570 | /* [1:1]: RG_LDO_VAUD28_HW0_OP_CFG */ |
| 571 | {0x1ACC, 0x1, 0x1, 1}, |
| 572 | /* [0:0]: RG_LDO_VIO28_SW_OP_EN */ |
| 573 | {0x1ADA, 0x1, 0x1, 0}, |
| 574 | /* [0:0]: RG_LDO_VIO18_SW_OP_EN */ |
| 575 | {0x1AEE, 0x1, 0x1, 0}, |
| 576 | /* [2:2]: RG_LDO_VFE28_HW1_OP_EN */ |
| 577 | {0x1C0A, 0x1, 0x1, 2}, |
| 578 | /* [2:2]: RG_LDO_VFE28_HW1_OP_CFG */ |
| 579 | {0x1C10, 0x0, 0x1, 2}, |
| 580 | /* [1:1]: RG_LDO_VDRAM2_HW0_OP_EN */ |
| 581 | {0x1B0A, 0x1, 0x1, 1}, |
| 582 | /* [1:1]: RG_LDO_VDRAM2_HW0_OP_CFG */ |
| 583 | {0x1B10, 0x1, 0x1, 1}, |
| 584 | /* [0:0]: RG_LDO_VMC_SW_OP_EN */ |
| 585 | {0x1CC6, 0x1, 0x1, 0}, |
| 586 | /* [0:0]: RG_LDO_VMCH_SW_OP_EN */ |
| 587 | {0x1CDA, 0x1, 0x1, 0}, |
| 588 | /* [0:0]: RG_LDO_VEMC_SW_OP_EN */ |
| 589 | {0x1B1E, 0x1, 0x1, 0}, |
| 590 | /* [0:0]: RG_LDO_VSIM1_SW_OP_EN */ |
| 591 | {0x1D4A, 0x1, 0x1, 0}, |
| 592 | /* [0:0]: RG_LDO_VSIM2_SW_OP_EN */ |
| 593 | {0x1D5E, 0x1, 0x1, 0}, |
| 594 | /* [0:0]: RG_LDO_VIBR_SW_OP_EN */ |
| 595 | {0x1D0A, 0x1, 0x1, 0}, |
| 596 | /* [1:1]: RG_LDO_VUSB_HW0_OP_EN */ |
| 597 | {0x1B32, 0x1, 0x1, 1}, |
| 598 | /* [1:1]: RG_LDO_VUSB_HW0_OP_CFG */ |
| 599 | {0x1B38, 0x1, 0x1, 1}, |
| 600 | /* [1:1]: RG_LDO_VUSB_HW0_OP_EN */ |
| 601 | {0x1B32, 0x1, 0x1, 1}, |
| 602 | /* [1:1]: RG_LDO_VUSB_HW0_OP_CFG */ |
| 603 | {0x1B38, 0x1, 0x1, 1}, |
| 604 | /* [1:1]: RG_LDO_VBIF28_HW0_OP_EN */ |
| 605 | {0x1DA0, 0x1, 0x1, 1}, |
| 606 | /* [1:1]: RG_LDO_VBIF28_HW0_OP_CFG */ |
| 607 | {0x1DA6, 0x0, 0x1, 1}, |
| 608 | |
| 609 | /* Deep idle setting */ |
| 610 | /* [0:0]: RG_BUCK_VPROC11_SW_OP_EN */ |
| 611 | {0x1390, 0x1, 0x1, 0}, |
| 612 | /* [0:0]: RG_BUCK_VCORE_SW_OP_EN */ |
| 613 | {0x1490, 0x1, 0x1, 0}, |
| 614 | /* [0:0]: RG_BUCK_VGPU_SW_OP_EN */ |
| 615 | {0x1510, 0x1, 0x1, 0}, |
| 616 | /* [0:0]: RG_BUCK_VMODEM_SW_OP_EN */ |
| 617 | {0x1590, 0x1, 0x1, 0}, |
| 618 | /* [0:0]: RG_BUCK_VS1_SW_OP_EN */ |
| 619 | {0x1690, 0x1, 0x1, 0}, |
| 620 | /* [3:3]: RG_BUCK_VS2_HW2_OP_EN */ |
| 621 | {0x1710, 0x1, 0x1, 3}, |
| 622 | /* [3:3]: RG_BUCK_VS2_HW2_OP_CFG */ |
| 623 | {0x1716, 0x1, 0x1, 3}, |
| 624 | /* [3:3]: RG_BUCK_VDRAM1_HW2_OP_EN */ |
| 625 | {0x1610, 0x1, 0x1, 3}, |
| 626 | /* [3:3]: RG_BUCK_VDRAM1_HW2_OP_CFG */ |
| 627 | {0x1616, 0x1, 0x1, 3}, |
| 628 | /* [0:0]: RG_BUCK_VPROC12_SW_OP_EN */ |
| 629 | {0x1410, 0x1, 0x1, 0}, |
| 630 | /* [0:0]: RG_LDO_VSRAM_GPU_SW_OP_EN */ |
| 631 | {0x1BD0, 0x1, 0x1, 0}, |
| 632 | /* [3:3]: RG_LDO_VSRAM_OTHERS_HW2_OP_EN */ |
| 633 | {0x1BAE, 0x1, 0x1, 3}, |
| 634 | /* [3:3]: RG_LDO_VSRAM_OTHERS_HW2_OP_CFG */ |
| 635 | {0x1BB4, 0x1, 0x1, 3}, |
| 636 | /* [0:0]: RG_LDO_VSRAM_PROC11_SW_OP_EN */ |
| 637 | {0x1B4E, 0x1, 0x1, 0}, |
| 638 | /* [3:3]: RG_LDO_VXO22_HW2_OP_EN */ |
| 639 | {0x1A8A, 0x1, 0x1, 3}, |
| 640 | /* [3:3]: RG_LDO_VXO22_HW2_OP_CFG */ |
| 641 | {0x1A90, 0x1, 0x1, 3}, |
| 642 | /* [2:2]: RG_LDO_VRF18_HW1_OP_EN */ |
| 643 | {0x1C1E, 0x1, 0x1, 2}, |
| 644 | /* [2:2]: RG_LDO_VRF18_HW1_OP_CFG */ |
| 645 | {0x1C24, 0x0, 0x1, 2}, |
| 646 | /* [2:2]: RG_LDO_VRF12_HW1_OP_EN */ |
| 647 | {0x1C32, 0x1, 0x1, 2}, |
| 648 | /* [2:2]: RG_LDO_VRF12_HW1_OP_CFG */ |
| 649 | {0x1C38, 0x0, 0x1, 2}, |
| 650 | /* [0:0]: RG_LDO_VEFUSE_SW_OP_EN */ |
| 651 | {0x1C46, 0x1, 0x1, 0}, |
| 652 | /* [0:0]: RG_LDO_VCN33_SW_OP_EN */ |
| 653 | {0x1D1E, 0x1, 0x1, 0}, |
| 654 | /* [0:0]: RG_LDO_VCN33_SW_OP_EN */ |
| 655 | {0x1D1E, 0x1, 0x1, 0}, |
| 656 | /* [0:0]: RG_LDO_VCN28_SW_OP_EN */ |
| 657 | {0x1D8A, 0x1, 0x1, 0}, |
| 658 | /* [0:0]: RG_LDO_VCN18_SW_OP_EN */ |
| 659 | {0x1C5A, 0x1, 0x1, 0}, |
| 660 | /* [0:0]: RG_LDO_VCAMA1_SW_OP_EN */ |
| 661 | {0x1C6E, 0x1, 0x1, 0}, |
| 662 | /* [0:0]: RG_LDO_VCAMD_SW_OP_EN */ |
| 663 | {0x1C9E, 0x1, 0x1, 0}, |
| 664 | /* [0:0]: RG_LDO_VCAMA2_SW_OP_EN */ |
| 665 | {0x1C8A, 0x1, 0x1, 0}, |
| 666 | /* [0:0]: RG_LDO_VSRAM_PROC12_SW_OP_EN */ |
| 667 | {0x1B90, 0x1, 0x1, 0}, |
| 668 | /* [0:0]: RG_LDO_VCAMIO_SW_OP_EN */ |
| 669 | {0x1CB2, 0x1, 0x1, 0}, |
| 670 | /* [0:0]: RG_LDO_VLDO28_SW_OP_EN */ |
| 671 | {0x1D34, 0x1, 0x1, 0}, |
| 672 | /* [0:0]: RG_LDO_VLDO28_SW_OP_EN */ |
| 673 | {0x1D34, 0x1, 0x1, 0}, |
| 674 | /* [3:3]: RG_LDO_VA12_HW2_OP_EN */ |
| 675 | {0x1A9E, 0x1, 0x1, 3}, |
| 676 | /* [3:3]: RG_LDO_VA12_HW2_OP_CFG */ |
| 677 | {0x1AA4, 0x1, 0x1, 3}, |
| 678 | /* [3:3]: RG_LDO_VAUX18_HW2_OP_EN */ |
| 679 | {0x1AB2, 0x1, 0x1, 3}, |
| 680 | /* [3:3]: RG_LDO_VAUX18_HW2_OP_CFG */ |
| 681 | {0x1AB8, 0x1, 0x1, 3}, |
| 682 | /* [0:0]: RG_LDO_VAUD28_SW_OP_EN */ |
| 683 | {0x1AC6, 0x1, 0x1, 0}, |
| 684 | /* [0:0]: RG_LDO_VIO28_SW_OP_EN */ |
| 685 | {0x1ADA, 0x1, 0x1, 0}, |
| 686 | /* [0:0]: RG_LDO_VIO18_SW_OP_EN */ |
| 687 | {0x1AEE, 0x1, 0x1, 0}, |
| 688 | /* [2:2]: RG_LDO_VFE28_HW1_OP_EN */ |
| 689 | {0x1C0A, 0x1, 0x1, 2}, |
| 690 | /* [2:2]: RG_LDO_VFE28_HW1_OP_CFG */ |
| 691 | {0x1C10, 0x0, 0x1, 2}, |
| 692 | /* [3:3]: RG_LDO_VDRAM2_HW2_OP_EN */ |
| 693 | {0x1B0A, 0x1, 0x1, 3}, |
| 694 | /* [3:3]: RG_LDO_VDRAM2_HW2_OP_CFG */ |
| 695 | {0x1B10, 0x1, 0x1, 3}, |
| 696 | /* [0:0]: RG_LDO_VMC_SW_OP_EN */ |
| 697 | {0x1CC6, 0x1, 0x1, 0}, |
| 698 | /* [0:0]: RG_LDO_VMCH_SW_OP_EN */ |
| 699 | {0x1CDA, 0x1, 0x1, 0}, |
| 700 | /* [0:0]: RG_LDO_VEMC_SW_OP_EN */ |
| 701 | {0x1B1E, 0x1, 0x1, 0}, |
| 702 | /* [0:0]: RG_LDO_VSIM1_SW_OP_EN */ |
| 703 | {0x1D4A, 0x1, 0x1, 0}, |
| 704 | /* [0:0]: RG_LDO_VSIM2_SW_OP_EN */ |
| 705 | {0x1D5E, 0x1, 0x1, 0}, |
| 706 | /* [0:0]: RG_LDO_VIBR_SW_OP_EN */ |
| 707 | {0x1D0A, 0x1, 0x1, 0}, |
| 708 | /* [3:3]: RG_LDO_VUSB_HW2_OP_EN */ |
| 709 | {0x1B32, 0x1, 0x1, 3}, |
| 710 | /* [3:3]: RG_LDO_VUSB_HW2_OP_CFG */ |
| 711 | {0x1B38, 0x1, 0x1, 3}, |
| 712 | /* [3:3]: RG_LDO_VUSB_HW2_OP_EN */ |
| 713 | {0x1B32, 0x1, 0x1, 3}, |
| 714 | /* [3:3]: RG_LDO_VUSB_HW2_OP_CFG */ |
| 715 | {0x1B38, 0x1, 0x1, 3}, |
| 716 | /* [3:3]: RG_LDO_VBIF28_HW2_OP_EN */ |
| 717 | {0x1DA0, 0x1, 0x1, 3}, |
| 718 | /* [3:3]: RG_LDO_VBIF28_HW2_OP_CFG */ |
| 719 | {0x1DA6, 0x0, 0x1, 3}, |
| 720 | }; |
| 721 | |
Hsin-Hsiung Wang | e804695 | 2019-07-10 21:31:34 +0800 | [diff] [blame] | 722 | static struct pmic_setting scp_setting[] = { |
| 723 | /* scp voltage initialization */ |
| 724 | /* [6:0]: RG_BUCK_VCORE_SSHUB_VOSEL */ |
| 725 | {0x14A6, 0x20, 0x7F, 0}, |
| 726 | /* [14:8]: RG_BUCK_VCORE_SSHUB_VOSEL_SLEEP */ |
| 727 | {0x14A6, 0x20, 0x7F, 8}, |
| 728 | /* [0:0]: RG_BUCK_VCORE_SSHUB_EN */ |
| 729 | {0x14A4, 0x1, 0x1, 0}, |
| 730 | /* [1:1]: RG_BUCK_VCORE_SSHUB_SLEEP_VOSEL_EN */ |
| 731 | {0x14A4, 0x0, 0x1, 1}, |
| 732 | /* [6:0]: RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL */ |
| 733 | {0x1BC6, 0x40, 0x7F, 0}, |
| 734 | /* [14:8]: RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SLEEP */ |
| 735 | {0x1BC6, 0x40, 0x7F, 8}, |
| 736 | /* [0:0]: RG_LDO_VSRAM_OTHERS_SSHUB_EN */ |
| 737 | {0x1BC4, 0x1, 0x1, 0}, |
| 738 | /* [1:1]: RG_LDO_VSRAM_OTHERS_SSHUB_SLEEP_VOSEL_EN */ |
| 739 | {0x1BC4, 0x0, 0x1, 1}, |
| 740 | /* [4:4]: RG_SRCVOLTEN_LP_EN */ |
| 741 | {0x134, 0x1, 0x1, 4}, |
| 742 | }; |
Hsin-Hsiung Wang | 0d0b7a1 | 2019-08-29 15:41:28 +0800 | [diff] [blame] | 743 | |
| 744 | static const int vddq_votrim[] = { |
| 745 | 0, -10000, -20000, -30000, -40000, -50000, -60000, -70000, |
| 746 | 80000, 70000, 60000, 50000, 40000, 30000, 20000, 10000, |
| 747 | }; |
| 748 | |
| 749 | static unsigned int pmic_read_efuse(int i) |
| 750 | { |
| 751 | unsigned int efuse_data = 0; |
| 752 | |
| 753 | /* 1. Enable efuse ctrl engine clock */ |
| 754 | pwrap_write_field(PMIC_TOP_CKHWEN_CON0_CLR, 0x1, 0x1, 2); |
| 755 | pwrap_write_field(PMIC_TOP_CKPDN_CON0_CLR, 0x1, 0x1, 4); |
| 756 | |
| 757 | /* 2. */ |
| 758 | pwrap_write_field(PMIC_OTP_CON11, 0x1, 0x1, 0); |
| 759 | |
| 760 | /* 3. Set row to read */ |
| 761 | pwrap_write_field(PMIC_OTP_CON0, i * 2, 0xFF, 0); |
| 762 | |
| 763 | /* 4. Toggle RG_OTP_RD_TRIG */ |
| 764 | if (pwrap_read_field(PMIC_OTP_CON8, 0x1, 0) == 0) |
| 765 | pwrap_write_field(PMIC_OTP_CON8, 0x1, 0x1, 0); |
| 766 | else |
| 767 | pwrap_write_field(PMIC_OTP_CON8, 0, 0x1, 0); |
| 768 | |
| 769 | /* 5. Polling RG_OTP_RD_BUSY = 0 */ |
| 770 | udelay(300); |
| 771 | while (pwrap_read_field(PMIC_OTP_CON13, 0x1, 0) == 1) |
| 772 | ; |
| 773 | |
| 774 | /* 6. Read RG_OTP_DOUT_SW */ |
| 775 | udelay(100); |
| 776 | efuse_data = pwrap_read_field(PMIC_OTP_CON12, 0xFFFF, 0); |
| 777 | |
| 778 | /* 7. Disable efuse ctrl engine clock */ |
| 779 | pwrap_write_field(PMIC_TOP_CKHWEN_CON0_SET, 0x1, 0x1, 2); |
| 780 | pwrap_write_field(PMIC_TOP_CKPDN_CON0_SET, 0x1, 0x1, 4); |
| 781 | |
| 782 | return efuse_data; |
| 783 | } |
| 784 | |
| 785 | static int pmic_get_efuse_votrim(void) |
| 786 | { |
| 787 | const unsigned int cali_efuse = pmic_read_efuse(104) & 0xF; |
Yu-Ping Wu | 42ec480 | 2019-10-22 16:54:44 +0800 | [diff] [blame] | 788 | assert(cali_efuse < ARRAY_SIZE(vddq_votrim)); |
Hsin-Hsiung Wang | 0d0b7a1 | 2019-08-29 15:41:28 +0800 | [diff] [blame] | 789 | return vddq_votrim[cali_efuse]; |
| 790 | } |
| 791 | |
Hsin-Hsiung Wang | 23b1afe | 2018-10-24 19:18:28 +0800 | [diff] [blame] | 792 | void pmic_set_power_hold(bool enable) |
| 793 | { |
| 794 | pwrap_write_field(PMIC_PWRHOLD, (enable) ? 1 : 0, 0x1, 0); |
| 795 | } |
| 796 | |
Hsin-Hsiung Wang | e804695 | 2019-07-10 21:31:34 +0800 | [diff] [blame] | 797 | void pmic_init_scp_voltage(void) |
| 798 | { |
| 799 | for (size_t i = 0; i < ARRAY_SIZE(scp_setting); i++) |
| 800 | pwrap_write_field( |
| 801 | scp_setting[i].addr, scp_setting[i].val, |
| 802 | scp_setting[i].mask, scp_setting[i].shift); |
| 803 | } |
| 804 | |
Hsin-Hsiung Wang | c10af29 | 2019-03-26 15:38:04 +0800 | [diff] [blame] | 805 | void pmic_set_vsim2_cali(unsigned int vsim2_mv) |
| 806 | { |
| 807 | u16 vsim2_reg, cali_mv; |
| 808 | |
| 809 | cali_mv = vsim2_mv % 100; |
| 810 | assert(cali_mv % 10 == 0); |
| 811 | |
| 812 | switch (vsim2_mv - cali_mv) { |
| 813 | case 1700: |
| 814 | vsim2_reg = 0x3; |
| 815 | break; |
| 816 | |
| 817 | case 1800: |
| 818 | vsim2_reg = 0x4; |
| 819 | break; |
| 820 | |
| 821 | case 2700: |
| 822 | vsim2_reg = 0x8; |
| 823 | break; |
| 824 | |
| 825 | case 3000: |
| 826 | vsim2_reg = 0xb; |
| 827 | break; |
| 828 | |
| 829 | case 3100: |
| 830 | vsim2_reg = 0xc; |
| 831 | break; |
| 832 | |
| 833 | default: |
Julius Werner | 3e034b6 | 2020-07-29 17:39:21 -0700 | [diff] [blame] | 834 | BUG(); |
Hsin-Hsiung Wang | c10af29 | 2019-03-26 15:38:04 +0800 | [diff] [blame] | 835 | return; |
| 836 | }; |
| 837 | |
| 838 | /* [11:8]=0x8, RG_VSIM2_VOSEL */ |
| 839 | pwrap_write_field(PMIC_VSIM2_ANA_CON0, vsim2_reg, 0xF, 8); |
| 840 | |
| 841 | /* [3:0], RG_VSIM2_VOCAL */ |
| 842 | pwrap_write_field(PMIC_VSIM2_ANA_CON0, cali_mv / 10, 0xF, 0); |
| 843 | } |
| 844 | |
Hsin-Hsiung Wang | 9168ab0 | 2019-08-29 14:56:25 +0800 | [diff] [blame] | 845 | unsigned int pmic_get_vcore_vol(void) |
| 846 | { |
| 847 | unsigned int vol_reg; |
| 848 | |
| 849 | vol_reg = pwrap_read_field(PMIC_VCORE_DBG0, 0x7F, 0); |
| 850 | return 500000 + vol_reg * 6250; |
| 851 | } |
| 852 | |
| 853 | void pmic_set_vcore_vol(unsigned int vcore_uv) |
| 854 | { |
| 855 | unsigned int vol_reg; |
| 856 | |
| 857 | assert(vcore_uv >= 500000); |
| 858 | assert(vcore_uv <= 1100000); |
| 859 | |
| 860 | vol_reg = (vcore_uv - 500000) / 6250; |
| 861 | |
| 862 | pwrap_write_field(PMIC_VCORE_OP_EN, 1, 0x7F, 0); |
| 863 | pwrap_write_field(PMIC_VCORE_VOSEL, vol_reg, 0x7F, 0); |
Yu-Ping Wu | ea4bda5 | 2019-10-23 16:51:26 +0800 | [diff] [blame] | 864 | udelay(1); |
Hsin-Hsiung Wang | 9168ab0 | 2019-08-29 14:56:25 +0800 | [diff] [blame] | 865 | } |
| 866 | |
Hsin-Hsiung Wang | 8d53137 | 2019-06-04 11:24:25 +0800 | [diff] [blame] | 867 | unsigned int pmic_get_vdram1_vol(void) |
| 868 | { |
| 869 | unsigned int vol_reg; |
| 870 | |
| 871 | vol_reg = pwrap_read_field(PMIC_VDRAM1_DBG0, 0x7F, 0); |
| 872 | return 500000 + vol_reg * 12500; |
| 873 | } |
| 874 | |
| 875 | void pmic_set_vdram1_vol(unsigned int vdram_uv) |
| 876 | { |
| 877 | unsigned int vol_reg; |
| 878 | |
| 879 | assert(vdram_uv >= 500000); |
| 880 | assert(vdram_uv <= 1300000); |
| 881 | |
| 882 | vol_reg = (vdram_uv - 500000) / 12500; |
| 883 | |
| 884 | pwrap_write_field(PMIC_VDRAM1_OP_EN, 1, 0x7F, 0); |
| 885 | pwrap_write_field(PMIC_VDRAM1_VOSEL, vol_reg, 0x7F, 0); |
Yu-Ping Wu | ea4bda5 | 2019-10-23 16:51:26 +0800 | [diff] [blame] | 886 | udelay(1); |
Hsin-Hsiung Wang | 8d53137 | 2019-06-04 11:24:25 +0800 | [diff] [blame] | 887 | } |
| 888 | |
Hsin-Hsiung Wang | 0d0b7a1 | 2019-08-29 15:41:28 +0800 | [diff] [blame] | 889 | unsigned int pmic_get_vddq_vol(void) |
| 890 | { |
| 891 | int efuse_votrim; |
| 892 | unsigned int cali_trim; |
| 893 | |
| 894 | if (!pwrap_read_field(PMIC_VDDQ_OP_EN, 0x1, 15)) |
| 895 | return 0; |
| 896 | |
| 897 | efuse_votrim = pmic_get_efuse_votrim(); |
| 898 | cali_trim = pwrap_read_field(PMIC_VDDQ_ELR_0, 0xF, 0); |
Yu-Ping Wu | 42ec480 | 2019-10-22 16:54:44 +0800 | [diff] [blame] | 899 | assert(cali_trim < ARRAY_SIZE(vddq_votrim)); |
Hsin-Hsiung Wang | 0d0b7a1 | 2019-08-29 15:41:28 +0800 | [diff] [blame] | 900 | return 600 * 1000 - efuse_votrim + vddq_votrim[cali_trim]; |
| 901 | } |
| 902 | |
| 903 | void pmic_set_vddq_vol(unsigned int vddq_uv) |
| 904 | { |
| 905 | int target_mv, dram2_ori_mv, cali_offset_uv, cali_trim; |
| 906 | |
| 907 | assert(vddq_uv >= 530000); |
| 908 | assert(vddq_uv <= 680000); |
| 909 | |
| 910 | /* Round down to multiple of 10 */ |
| 911 | target_mv = (vddq_uv / 1000) / 10 * 10; |
| 912 | |
| 913 | dram2_ori_mv = 600 - pmic_get_efuse_votrim() / 1000; |
| 914 | cali_offset_uv = 1000 * (target_mv - dram2_ori_mv); |
| 915 | |
| 916 | if (cali_offset_uv >= 80000) |
| 917 | cali_trim = 8; |
| 918 | else if (cali_offset_uv <= -70000) |
| 919 | cali_trim = 7; |
| 920 | else { |
| 921 | cali_trim = 0; |
Yu-Ping Wu | 42ec480 | 2019-10-22 16:54:44 +0800 | [diff] [blame] | 922 | while (cali_trim < ARRAY_SIZE(vddq_votrim) && |
Hsin-Hsiung Wang | 0d0b7a1 | 2019-08-29 15:41:28 +0800 | [diff] [blame] | 923 | vddq_votrim[cali_trim] != cali_offset_uv) |
| 924 | ++cali_trim; |
Yu-Ping Wu | 42ec480 | 2019-10-22 16:54:44 +0800 | [diff] [blame] | 925 | assert(cali_trim < ARRAY_SIZE(vddq_votrim)); |
Hsin-Hsiung Wang | 0d0b7a1 | 2019-08-29 15:41:28 +0800 | [diff] [blame] | 926 | } |
| 927 | |
| 928 | pwrap_write_field(PMIC_TOP_TMA_KEY, 0x9CA7, 0xFFFF, 0); |
| 929 | pwrap_write_field(PMIC_VDDQ_ELR_0, cali_trim, 0xF, 0); |
| 930 | pwrap_write_field(PMIC_TOP_TMA_KEY, 0, 0xFFFF, 0); |
| 931 | udelay(1); |
| 932 | } |
| 933 | |
Hsin-Hsiung Wang | 23b1afe | 2018-10-24 19:18:28 +0800 | [diff] [blame] | 934 | static void pmic_wdt_set(void) |
| 935 | { |
| 936 | /* [5]=1, RG_WDTRSTB_DEB */ |
| 937 | pwrap_write_field(PMIC_TOP_RST_MISC_SET, 0x0020, 0xFFFF, 0); |
| 938 | /* [1]=0, RG_WDTRSTB_MODE */ |
| 939 | pwrap_write_field(PMIC_TOP_RST_MISC_CLR, 0x0002, 0xFFFF, 0); |
| 940 | /* [0]=1, RG_WDTRSTB_EN */ |
| 941 | pwrap_write_field(PMIC_TOP_RST_MISC_SET, 0x0001, 0xFFFF, 0); |
| 942 | } |
| 943 | |
| 944 | static void mt6358_init_setting(void) |
| 945 | { |
| 946 | for (size_t i = 0; i < ARRAY_SIZE(init_setting); i++) |
| 947 | pwrap_write_field( |
| 948 | init_setting[i].addr, init_setting[i].val, |
| 949 | init_setting[i].mask, init_setting[i].shift); |
| 950 | } |
| 951 | |
| 952 | static void wk_sleep_voltage_by_ddr(void) |
| 953 | { |
| 954 | if (pwrap_read_field(PMIC_VM_MODE, 0x3, 0) == 0x2) |
| 955 | pwrap_write_field(PMIC_VDRAM1_VOSEL_SLEEP, 0x3A, 0x7F, 0); |
| 956 | } |
| 957 | |
| 958 | static void wk_power_down_seq(void) |
| 959 | { |
| 960 | /* Write TMA KEY with magic number */ |
| 961 | pwrap_write_field(PMIC_TOP_TMA_KEY, 0x9CA7, 0xFFFF, 0); |
| 962 | /* Set VPROC12 sequence to VA12 */ |
| 963 | pwrap_write_field(PMIC_CPSDSA4, 0xA, 0x1F, 0); |
| 964 | pwrap_write_field(PMIC_TOP_TMA_KEY, 0x0, 0xFFFF, 0); |
| 965 | } |
| 966 | |
| 967 | static void mt6358_lp_setting(void) |
| 968 | { |
| 969 | for (size_t i = 0; i < ARRAY_SIZE(lp_setting); i++) |
| 970 | pwrap_write_field( |
| 971 | lp_setting[i].addr, lp_setting[i].val, |
| 972 | lp_setting[i].mask, lp_setting[i].shift); |
| 973 | } |
| 974 | |
| 975 | void mt6358_init(void) |
| 976 | { |
Tristan Shieh | b75f493 | 2019-04-29 09:12:54 +0800 | [diff] [blame] | 977 | struct stopwatch voltage_settled; |
| 978 | |
Hsin-Hsiung Wang | 23b1afe | 2018-10-24 19:18:28 +0800 | [diff] [blame] | 979 | if (pwrap_init()) |
| 980 | die("ERROR - Failed to initialize pmic wrap!"); |
| 981 | |
| 982 | pmic_set_power_hold(true); |
| 983 | pmic_wdt_set(); |
| 984 | mt6358_init_setting(); |
Tristan Shieh | b75f493 | 2019-04-29 09:12:54 +0800 | [diff] [blame] | 985 | stopwatch_init_usecs_expire(&voltage_settled, 200); |
Hsin-Hsiung Wang | 23b1afe | 2018-10-24 19:18:28 +0800 | [diff] [blame] | 986 | wk_sleep_voltage_by_ddr(); |
| 987 | wk_power_down_seq(); |
| 988 | mt6358_lp_setting(); |
Tristan Shieh | b75f493 | 2019-04-29 09:12:54 +0800 | [diff] [blame] | 989 | while (!stopwatch_expired(&voltage_settled)) |
| 990 | /* wait for voltages to settle */; |
Hsin-Hsiung Wang | 23b1afe | 2018-10-24 19:18:28 +0800 | [diff] [blame] | 991 | } |