| Angel Pons | e67ab18 | 2020-04-04 18:51:11 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 2 | |
| Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
| Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 4 | #include <soc/mcucfg.h> |
| 5 | #include <soc/timer.h> |
| 6 | |
| Tristan Shieh | 4c8d487 | 2018-06-06 13:35:12 +0800 | [diff] [blame] | 7 | void timer_prepare(void) |
| Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 8 | { |
| 9 | /* Set XGPT_IDX to 0, then the bit field of XGPT_CTL will be programmed |
| 10 | * with following definition. |
| 11 | * |
| 12 | * [10: 8] Clock mode |
| 13 | * 100: 26Mhz / 4 |
| 14 | * 010: 26Mhz / 2 |
| 15 | * 001: 26Mhz |
| 16 | * [ 1: 1] Halt-on-debug enable bit |
| 17 | * [ 0: 0] XGPT enable bit |
| 18 | */ |
| 19 | write32(&mt8173_mcucfg->xgpt_idx, 0); |
| 20 | /* Set clock mode to 13Mhz and enable XGPT */ |
| Tristan Shieh | a76e654 | 2019-04-08 11:01:40 +0800 | [diff] [blame] | 21 | write32(&mt8173_mcucfg->xgpt_ctl, (0x1 | ((26 / GPT_MHZ) << 8))); |
| Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 22 | } |