Patrick Georgi | c49d7a3 | 2020-05-08 22:50:46 +0200 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 2 | |
| 3 | ifeq ($(CONFIG_SOC_MEDIATEK_MT8173),y) |
| 4 | |
| 5 | bootblock-y += bootblock.c |
Yidi Lin | b17e805 | 2020-12-28 21:59:11 +0800 | [diff] [blame] | 6 | bootblock-$(CONFIG_SPI_FLASH) += ../common/flash_controller.c |
Qii Wang | 30e9bc56 | 2019-01-18 09:53:01 +0800 | [diff] [blame] | 7 | bootblock-y += ../common/i2c.c i2c.c |
Tristan Shieh | 17180af | 2018-07-02 17:20:13 +0800 | [diff] [blame] | 8 | bootblock-y += ../common/pll.c pll.c |
Tristan Shieh | 86d0d6e | 2018-07-16 20:16:40 +0800 | [diff] [blame] | 9 | bootblock-y += ../common/spi.c spi.c |
Tristan Shieh | 362a734 | 2018-06-06 14:03:22 +0800 | [diff] [blame] | 10 | bootblock-y += ../common/timer.c |
Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 11 | bootblock-y += timer.c |
| 12 | |
Nico Huber | 755db95 | 2018-11-11 01:42:17 +0100 | [diff] [blame] | 13 | bootblock-y += ../common/uart.c |
Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 14 | |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 15 | bootblock-y += ../common/gpio.c gpio.c gpio_init.c |
| 16 | bootblock-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c |
Tristan Shieh | e6a03e0 | 2019-01-28 15:31:50 +0800 | [diff] [blame] | 17 | bootblock-y += ../common/wdt.c ../common/reset.c |
Tristan Shieh | c645a5a | 2018-07-04 13:37:39 +0800 | [diff] [blame] | 18 | bootblock-y += ../common/mmu_operations.c mmu_operations.c |
henryc.chen | fb622cc | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 19 | |
Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 20 | ################################################################################ |
| 21 | |
Qii Wang | 30e9bc56 | 2019-01-18 09:53:01 +0800 | [diff] [blame] | 22 | verstage-y += ../common/i2c.c i2c.c |
Tristan Shieh | 86d0d6e | 2018-07-16 20:16:40 +0800 | [diff] [blame] | 23 | verstage-y += ../common/spi.c spi.c |
Itamar | 49cb61b | 2015-07-31 17:10:46 +0800 | [diff] [blame] | 24 | |
Nico Huber | 755db95 | 2018-11-11 01:42:17 +0100 | [diff] [blame] | 25 | verstage-y += ../common/uart.c |
Itamar | 49cb61b | 2015-07-31 17:10:46 +0800 | [diff] [blame] | 26 | |
Tristan Shieh | 362a734 | 2018-06-06 14:03:22 +0800 | [diff] [blame] | 27 | verstage-y += ../common/timer.c |
Itamar | 49cb61b | 2015-07-31 17:10:46 +0800 | [diff] [blame] | 28 | verstage-y += timer.c |
Tristan Shieh | e6a03e0 | 2019-01-28 15:31:50 +0800 | [diff] [blame] | 29 | verstage-y += ../common/wdt.c ../common/reset.c |
Yidi Lin | b17e805 | 2020-12-28 21:59:11 +0800 | [diff] [blame] | 30 | verstage-$(CONFIG_SPI_FLASH) += ../common/flash_controller.c |
Tristan Shieh | 71d227b | 2018-07-09 18:59:32 +0800 | [diff] [blame] | 31 | verstage-y += ../common/gpio.c gpio.c |
Itamar | 49cb61b | 2015-07-31 17:10:46 +0800 | [diff] [blame] | 32 | |
| 33 | ################################################################################ |
| 34 | |
Yidi Lin | b17e805 | 2020-12-28 21:59:11 +0800 | [diff] [blame] | 35 | romstage-$(CONFIG_SPI_FLASH) += ../common/flash_controller.c |
Tristan Shieh | 17180af | 2018-07-02 17:20:13 +0800 | [diff] [blame] | 36 | romstage-y += ../common/pll.c pll.c |
Tristan Shieh | 362a734 | 2018-06-06 14:03:22 +0800 | [diff] [blame] | 37 | romstage-y += ../common/timer.c |
Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 38 | romstage-y += timer.c |
Qii Wang | 30e9bc56 | 2019-01-18 09:53:01 +0800 | [diff] [blame] | 39 | romstage-y += ../common/i2c.c i2c.c |
Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 40 | |
Nico Huber | 755db95 | 2018-11-11 01:42:17 +0100 | [diff] [blame] | 41 | romstage-y += ../common/uart.c |
Tristan Shieh | 362a734 | 2018-06-06 14:03:22 +0800 | [diff] [blame] | 42 | romstage-y += ../common/cbmem.c |
Tristan Shieh | 71d227b | 2018-07-09 18:59:32 +0800 | [diff] [blame] | 43 | romstage-y += ../common/gpio.c gpio.c |
Tristan Shieh | 86d0d6e | 2018-07-16 20:16:40 +0800 | [diff] [blame] | 44 | romstage-y += ../common/spi.c spi.c |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 45 | romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c |
Peter Kao | da1e02a | 2015-07-31 17:11:14 +0800 | [diff] [blame] | 46 | romstage-y += memory.c |
| 47 | romstage-y += emi.c dramc_pi_basic_api.c dramc_pi_calibration_api.c |
Tristan Shieh | 79b990d | 2018-08-10 14:46:31 +0800 | [diff] [blame] | 48 | romstage-$(CONFIG_MEMORY_TEST) += ../common/memory_test.c |
Tristan Shieh | c645a5a | 2018-07-04 13:37:39 +0800 | [diff] [blame] | 49 | romstage-y += ../common/mmu_operations.c mmu_operations.c |
Ran Bi | 47d46d0 | 2018-10-26 15:18:09 +0800 | [diff] [blame] | 50 | romstage-y += ../common/rtc.c rtc.c |
Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 51 | |
| 52 | ################################################################################ |
| 53 | |
Arthur Heymans | d05f57c | 2019-10-23 18:54:48 +0200 | [diff] [blame] | 54 | ramstage-y += emi.c |
Tristan Shieh | 86d0d6e | 2018-07-16 20:16:40 +0800 | [diff] [blame] | 55 | ramstage-y += ../common/spi.c spi.c |
Yidi Lin | b17e805 | 2020-12-28 21:59:11 +0800 | [diff] [blame] | 56 | ramstage-$(CONFIG_SPI_FLASH) += ../common/flash_controller.c |
Tristan Shieh | 5da0029 | 2018-06-12 15:09:37 +0800 | [diff] [blame] | 57 | ramstage-y += soc.c ../common/mtcmos.c |
Tristan Shieh | 362a734 | 2018-06-06 14:03:22 +0800 | [diff] [blame] | 58 | ramstage-y += ../common/timer.c |
Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 59 | ramstage-y += timer.c |
Nico Huber | 755db95 | 2018-11-11 01:42:17 +0100 | [diff] [blame] | 60 | ramstage-y += ../common/uart.c |
Qii Wang | 30e9bc56 | 2019-01-18 09:53:01 +0800 | [diff] [blame] | 61 | ramstage-y += ../common/i2c.c i2c.c |
| 62 | ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c |
henryc.chen | 7c54d2a | 2016-03-02 15:49:52 +0800 | [diff] [blame] | 63 | ramstage-y += mt6311.c |
henryc.chen | 0bb292e | 2016-03-02 15:51:44 +0800 | [diff] [blame] | 64 | ramstage-y += da9212.c |
Tristan Shieh | 71d227b | 2018-07-09 18:59:32 +0800 | [diff] [blame] | 65 | ramstage-y += ../common/gpio.c gpio.c |
Tristan Shieh | e6a03e0 | 2019-01-28 15:31:50 +0800 | [diff] [blame] | 66 | ramstage-y += ../common/wdt.c ../common/reset.c |
Tristan Shieh | 17180af | 2018-07-02 17:20:13 +0800 | [diff] [blame] | 67 | ramstage-y += ../common/pll.c pll.c |
Ran Bi | 47d46d0 | 2018-10-26 15:18:09 +0800 | [diff] [blame] | 68 | ramstage-y += ../common/rtc.c rtc.c |
Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 69 | |
Tristan Shieh | 2234346 | 2018-09-26 13:33:36 +0800 | [diff] [blame] | 70 | ramstage-y += ../common/usb.c usb.c |
Chunfeng Yun | f764d14 | 2015-07-31 17:11:08 +0800 | [diff] [blame] | 71 | |
Hung-Te Lin | 7ece246 | 2019-08-05 03:08:57 +0800 | [diff] [blame] | 72 | ramstage-y += ../common/ddp.c ddp.c |
Hung-Te Lin | c59fbf2 | 2019-08-07 08:00:58 +0800 | [diff] [blame] | 73 | ramstage-y += ../common/dsi.c dsi.c |
Jitao Shi | 4a04a7b | 2016-01-08 16:02:13 +0800 | [diff] [blame] | 74 | |
Jimmy Huang | c541134 | 2016-03-05 10:25:05 +0800 | [diff] [blame] | 75 | BL31_MAKEARGS += PLAT=mt8173 |
Jimmy Huang | f3570d2 | 2015-07-31 17:11:00 +0800 | [diff] [blame] | 76 | |
Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 77 | ################################################################################ |
| 78 | |
Yidi Lin | 8e76f34 | 2015-07-31 17:10:48 +0800 | [diff] [blame] | 79 | # Generate the actual coreboot bootblock code |
| 80 | $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin |
| 81 | ./util/mtkheader/gen-bl-img.py mt8173 sf $< $@ |
| 82 | |
Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 83 | CPPFLAGS_common += -Isrc/soc/mediatek/mt8173/include |
Tristan Shieh | 362a734 | 2018-06-06 14:03:22 +0800 | [diff] [blame] | 84 | CPPFLAGS_common += -Isrc/soc/mediatek/common/include |
Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 85 | |
| 86 | endif |