blob: e824e54e14d4ff810d80508cacadba75b164c8db [file] [log] [blame]
Patrick Georgic49d7a32020-05-08 22:50:46 +02001## SPDX-License-Identifier: GPL-2.0-only
Yidi Lin3d7b6062015-07-31 17:10:40 +08002
3ifeq ($(CONFIG_SOC_MEDIATEK_MT8173),y)
4
5bootblock-y += bootblock.c
Yidi Linb17e8052020-12-28 21:59:11 +08006bootblock-$(CONFIG_SPI_FLASH) += ../common/flash_controller.c
Qii Wang30e9bc562019-01-18 09:53:01 +08007bootblock-y += ../common/i2c.c i2c.c
Tristan Shieh17180af2018-07-02 17:20:13 +08008bootblock-y += ../common/pll.c pll.c
Tristan Shieh86d0d6e2018-07-16 20:16:40 +08009bootblock-y += ../common/spi.c spi.c
Tristan Shieh362a7342018-06-06 14:03:22 +080010bootblock-y += ../common/timer.c
Yidi Lin3d7b6062015-07-31 17:10:40 +080011bootblock-y += timer.c
12
Nico Huber755db952018-11-11 01:42:17 +010013bootblock-y += ../common/uart.c
Yidi Lin3d7b6062015-07-31 17:10:40 +080014
Tristan Shiehab1b83d2018-11-01 18:01:50 +080015bootblock-y += ../common/gpio.c gpio.c gpio_init.c
16bootblock-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c
Tristan Shiehe6a03e02019-01-28 15:31:50 +080017bootblock-y += ../common/wdt.c ../common/reset.c
Tristan Shiehc645a5a2018-07-04 13:37:39 +080018bootblock-y += ../common/mmu_operations.c mmu_operations.c
henryc.chenfb622cc2015-07-31 17:10:52 +080019
Yidi Lin3d7b6062015-07-31 17:10:40 +080020################################################################################
21
Qii Wang30e9bc562019-01-18 09:53:01 +080022verstage-y += ../common/i2c.c i2c.c
Tristan Shieh86d0d6e2018-07-16 20:16:40 +080023verstage-y += ../common/spi.c spi.c
Itamar49cb61b2015-07-31 17:10:46 +080024
Nico Huber755db952018-11-11 01:42:17 +010025verstage-y += ../common/uart.c
Itamar49cb61b2015-07-31 17:10:46 +080026
Tristan Shieh362a7342018-06-06 14:03:22 +080027verstage-y += ../common/timer.c
Itamar49cb61b2015-07-31 17:10:46 +080028verstage-y += timer.c
Tristan Shiehe6a03e02019-01-28 15:31:50 +080029verstage-y += ../common/wdt.c ../common/reset.c
Yidi Linb17e8052020-12-28 21:59:11 +080030verstage-$(CONFIG_SPI_FLASH) += ../common/flash_controller.c
Tristan Shieh71d227b2018-07-09 18:59:32 +080031verstage-y += ../common/gpio.c gpio.c
Itamar49cb61b2015-07-31 17:10:46 +080032
33################################################################################
34
Yidi Linb17e8052020-12-28 21:59:11 +080035romstage-$(CONFIG_SPI_FLASH) += ../common/flash_controller.c
Tristan Shieh17180af2018-07-02 17:20:13 +080036romstage-y += ../common/pll.c pll.c
Tristan Shieh362a7342018-06-06 14:03:22 +080037romstage-y += ../common/timer.c
Yidi Lin3d7b6062015-07-31 17:10:40 +080038romstage-y += timer.c
Qii Wang30e9bc562019-01-18 09:53:01 +080039romstage-y += ../common/i2c.c i2c.c
Yidi Lin3d7b6062015-07-31 17:10:40 +080040
Nico Huber755db952018-11-11 01:42:17 +010041romstage-y += ../common/uart.c
Tristan Shieh362a7342018-06-06 14:03:22 +080042romstage-y += ../common/cbmem.c
Tristan Shieh71d227b2018-07-09 18:59:32 +080043romstage-y += ../common/gpio.c gpio.c
Tristan Shieh86d0d6e2018-07-16 20:16:40 +080044romstage-y += ../common/spi.c spi.c
Tristan Shiehab1b83d2018-11-01 18:01:50 +080045romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c
Peter Kaoda1e02a2015-07-31 17:11:14 +080046romstage-y += memory.c
47romstage-y += emi.c dramc_pi_basic_api.c dramc_pi_calibration_api.c
Tristan Shieh79b990d2018-08-10 14:46:31 +080048romstage-$(CONFIG_MEMORY_TEST) += ../common/memory_test.c
Tristan Shiehc645a5a2018-07-04 13:37:39 +080049romstage-y += ../common/mmu_operations.c mmu_operations.c
Ran Bi47d46d02018-10-26 15:18:09 +080050romstage-y += ../common/rtc.c rtc.c
Yidi Lin3d7b6062015-07-31 17:10:40 +080051
52################################################################################
53
Arthur Heymansd05f57c2019-10-23 18:54:48 +020054ramstage-y += emi.c
Tristan Shieh86d0d6e2018-07-16 20:16:40 +080055ramstage-y += ../common/spi.c spi.c
Yidi Linb17e8052020-12-28 21:59:11 +080056ramstage-$(CONFIG_SPI_FLASH) += ../common/flash_controller.c
Tristan Shieh5da00292018-06-12 15:09:37 +080057ramstage-y += soc.c ../common/mtcmos.c
Tristan Shieh362a7342018-06-06 14:03:22 +080058ramstage-y += ../common/timer.c
Yidi Lin3d7b6062015-07-31 17:10:40 +080059ramstage-y += timer.c
Nico Huber755db952018-11-11 01:42:17 +010060ramstage-y += ../common/uart.c
Qii Wang30e9bc562019-01-18 09:53:01 +080061ramstage-y += ../common/i2c.c i2c.c
62ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c
henryc.chen7c54d2a2016-03-02 15:49:52 +080063ramstage-y += mt6311.c
henryc.chen0bb292e2016-03-02 15:51:44 +080064ramstage-y += da9212.c
Tristan Shieh71d227b2018-07-09 18:59:32 +080065ramstage-y += ../common/gpio.c gpio.c
Tristan Shiehe6a03e02019-01-28 15:31:50 +080066ramstage-y += ../common/wdt.c ../common/reset.c
Tristan Shieh17180af2018-07-02 17:20:13 +080067ramstage-y += ../common/pll.c pll.c
Ran Bi47d46d02018-10-26 15:18:09 +080068ramstage-y += ../common/rtc.c rtc.c
Yidi Lin3d7b6062015-07-31 17:10:40 +080069
Tristan Shieh22343462018-09-26 13:33:36 +080070ramstage-y += ../common/usb.c usb.c
Chunfeng Yunf764d142015-07-31 17:11:08 +080071
Hung-Te Lin7ece2462019-08-05 03:08:57 +080072ramstage-y += ../common/ddp.c ddp.c
Hung-Te Linc59fbf22019-08-07 08:00:58 +080073ramstage-y += ../common/dsi.c dsi.c
Jitao Shi4a04a7b2016-01-08 16:02:13 +080074
Jimmy Huangc5411342016-03-05 10:25:05 +080075BL31_MAKEARGS += PLAT=mt8173
Jimmy Huangf3570d22015-07-31 17:11:00 +080076
Yidi Lin3d7b6062015-07-31 17:10:40 +080077################################################################################
78
Yidi Lin8e76f342015-07-31 17:10:48 +080079# Generate the actual coreboot bootblock code
80$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
81 ./util/mtkheader/gen-bl-img.py mt8173 sf $< $@
82
Yidi Lin3d7b6062015-07-31 17:10:40 +080083CPPFLAGS_common += -Isrc/soc/mediatek/mt8173/include
Tristan Shieh362a7342018-06-06 14:03:22 +080084CPPFLAGS_common += -Isrc/soc/mediatek/common/include
Yidi Lin3d7b6062015-07-31 17:10:40 +080085
86endif