Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | #include <assert.h> |
Lean Sheng Tan | 5cd7579 | 2021-06-09 13:58:12 -0700 | [diff] [blame] | 3 | #include <cbfs.h> |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 4 | #include <console/console.h> |
| 5 | #include <device/device.h> |
| 6 | #include <fsp/api.h> |
| 7 | #include <fsp/ppi/mp_service_ppi.h> |
| 8 | #include <fsp/util.h> |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 9 | #include <option.h> |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 10 | #include <intelblocks/lpss.h> |
Lean Sheng Tan | 58ec51c | 2021-06-09 06:51:22 -0700 | [diff] [blame] | 11 | #include <intelblocks/pmclib.h> |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 12 | #include <intelblocks/xdci.h> |
| 13 | #include <intelpch/lockdown.h> |
| 14 | #include <soc/intel/common/vbt.h> |
| 15 | #include <soc/pci_devs.h> |
| 16 | #include <soc/ramstage.h> |
| 17 | #include <soc/soc_chip.h> |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 18 | #include <types.h> |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 19 | |
Lean Sheng Tan | c6c5443 | 2021-05-30 09:08:35 -0700 | [diff] [blame] | 20 | /* SATA DEVSLP idle timeout default values */ |
| 21 | #define DEF_DMVAL 15 |
| 22 | #define DEF_DITOVAL_MS 625 |
| 23 | |
| 24 | /* Native function controls pads termination */ |
| 25 | #define GPIO_TERM_NATIVE 0x1F |
| 26 | |
Lean Sheng Tan | a96be27 | 2021-06-08 21:41:42 -0700 | [diff] [blame] | 27 | /* PM related values */ |
| 28 | /* Imon offset is defined in 1/1000 increments */ |
| 29 | #define IMON_OFFSET 1 |
| 30 | /* Policy Imon slope is defined in 1/100 increments */ |
| 31 | #define IMON_SLOPE 100 |
| 32 | /* Thermal Design Current current limit in 1/8A units */ |
| 33 | #define TDC_CURRENT_LIMIT_MAX 112 |
| 34 | /* AcLoadline in 1/100 mOhms */ |
| 35 | #define AC_LOADLINE_LANE_0_MAX 112 |
| 36 | #define AC_LOADLINE_LANE_1_MAX 3 |
| 37 | /* DcLoadline in 1/100 mOhms */ |
| 38 | #define DC_LOADLINE_LANE_0_MAX 92 |
| 39 | #define DC_LOADLINE_LANE_1_MAX 3 |
| 40 | /* VR Icc Max limit. 0-255A in 1/4 A units */ |
| 41 | #define ICC_LIMIT_MAX 104 |
| 42 | /* Core Ratio Limit: For overclocking part: LFM to Fused */ |
| 43 | #define CORE_RATIO_LIMIT 0x13 |
| 44 | |
Lean Sheng Tan | 9420e28 | 2021-05-27 22:48:33 -0700 | [diff] [blame] | 45 | /* |
| 46 | * Chip config parameter PcieRpL1Substates uses (UPD value + 1) |
| 47 | * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. |
| 48 | * In order to ensure that mainboard setting does not disable L1 substates |
| 49 | * incorrectly, chip config parameter values are offset by 1 with 0 meaning |
| 50 | * use FSP UPD default. get_l1_substate_control() ensures that the right UPD |
| 51 | * value is set in fsp_params. |
| 52 | * 0: Use FSP UPD default |
| 53 | * 1: Disable L1 substates |
| 54 | * 2: Use L1.1 |
| 55 | * 3: Use L1.2 (FSP UPD default) |
| 56 | */ |
| 57 | static int get_l1_substate_control(enum L1_substates_control ctl) |
| 58 | { |
| 59 | if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) |
| 60 | ctl = L1_SS_L1_2; |
| 61 | return ctl - 1; |
| 62 | } |
| 63 | |
Lean Sheng Tan | 8d4e67d | 2021-06-25 11:23:03 -0700 | [diff] [blame] | 64 | static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg, |
| 65 | const struct soc_intel_elkhartlake_config *config) |
| 66 | { |
| 67 | s_cfg->PchFivrExtV1p05RailEnabledStates = config->fivr.v1p05_state; |
| 68 | s_cfg->PchFivrExtV1p05RailSupportedVoltageStates = config->fivr.v1p05_rail; |
| 69 | s_cfg->PchFivrExtVnnRailEnabledStates = config->fivr.vnn_state; |
| 70 | s_cfg->PchFivrExtVnnRailSupportedVoltageStates = config->fivr.vnn_rail; |
| 71 | s_cfg->PchFivrExtVnnRailSxEnabledStates = config->fivr.vnn_sx_state; |
| 72 | s_cfg->PchFivrVccinAuxLowToHighCurModeVolTranTime = config->fivr.vcc_low_high_us; |
| 73 | s_cfg->PchFivrVccinAuxRetToHighCurModeVolTranTime = config->fivr.vcc_ret_high_us; |
| 74 | s_cfg->PchFivrVccinAuxRetToLowCurModeVolTranTime = config->fivr.vcc_ret_low_us; |
| 75 | s_cfg->PchFivrVccinAuxOffToHighCurModeVolTranTime = config->fivr.vcc_off_high_us; |
| 76 | /* Convert mV to number of 2.5 mV increments */ |
| 77 | s_cfg->PchFivrExtVnnRailSxVoltage = (config->fivr.vnn_sx_mv * 10) / 25; |
| 78 | s_cfg->PchFivrExtV1p05RailIccMaximum = config->fivr.v1p05_icc_max_ma; |
| 79 | s_cfg->FivrSpreadSpectrum = config->fivr.spread_spectrum; |
| 80 | } |
| 81 | |
Lean Sheng Tan | 7760fe4 | 2021-07-27 04:28:20 -0700 | [diff] [blame] | 82 | static void fill_fsps_tsn_params(FSP_S_CONFIG *params, |
| 83 | const struct soc_intel_elkhartlake_config *config) |
| 84 | { |
| 85 | /* |
| 86 | * Currently EHL TSN GBE only supports link speed with 2 type of |
| 87 | * PCH XTAL frequency: 24 MHz and 38.4 MHz. |
| 88 | * These are the config values for PchTsnGbeLinkSpeed in FSP-S UPD: |
| 89 | * 0: 24MHz 2.5Gbps, 1: 24MHz 1Gbps, 2: 38.4MHz 2.5Gbps, |
| 90 | * 3: 38.4MHz 1Gbps |
| 91 | */ |
| 92 | int xtal_freq_enum = pmc_get_xtal_freq(); |
| 93 | if ((xtal_freq_enum != XTAL_24_MHZ) && (xtal_freq_enum != XTAL_38_4_MHZ)) { |
| 94 | printk(BIOS_ERR, "XTAL not supported. Disabling All TSN GBE ports.\n"); |
| 95 | params->PchTsnEnable = 0; |
| 96 | params->PchPseGbeEnable[0] = 0; |
| 97 | params->PchPseGbeEnable[1] = 0; |
| 98 | devfn_disable(pci_root_bus(), PCH_DEVFN_GBE); |
| 99 | devfn_disable(pci_root_bus(), PCH_DEVFN_PSEGBE0); |
| 100 | devfn_disable(pci_root_bus(), PCH_DEVFN_PSEGBE1); |
| 101 | } |
| 102 | /* |
| 103 | * PCH TSN settings: |
| 104 | * Due to EHL GBE comes with time sensitive networking (TSN) |
| 105 | * capability integrated, EHL FSP is using PchTsnEnable instead of |
| 106 | * usual PchLanEnable flag for GBE control. Hence, force |
| 107 | * PchLanEnable to disable to avoid it being used in the future. |
| 108 | */ |
| 109 | params->PchLanEnable = 0x0; |
| 110 | params->PchTsnEnable = is_devfn_enabled(PCH_DEVFN_GBE); |
| 111 | if (params->PchTsnEnable) { |
| 112 | params->PchTsnGbeSgmiiEnable = config->PchTsnGbeSgmiiEnable; |
| 113 | params->PchTsnGbeMultiVcEnable = config->PchTsnGbeMultiVcEnable; |
| 114 | params->PchTsnGbeLinkSpeed = (config->PchTsnGbeLinkSpeed) + xtal_freq_enum; |
| 115 | } |
| 116 | |
| 117 | /* PSE TSN settings */ |
| 118 | if (!CONFIG(PSE_ENABLE)) |
| 119 | return; |
| 120 | for (unsigned int i = 0; i < MAX_PSE_TSN_PORTS; i++) { |
| 121 | switch (i) { |
| 122 | case 0: |
| 123 | params->PchPseGbeEnable[i] = is_devfn_enabled(PCH_DEVFN_PSEGBE0) ? |
| 124 | Host_Owned : config->PseGbeOwn[0]; |
| 125 | break; |
| 126 | case 1: |
| 127 | params->PchPseGbeEnable[i] = is_devfn_enabled(PCH_DEVFN_PSEGBE1) ? |
| 128 | Host_Owned : config->PseGbeOwn[i]; |
| 129 | break; |
| 130 | default: |
| 131 | break; |
| 132 | } |
| 133 | if (params->PchPseGbeEnable[i]) { |
| 134 | params->PseTsnGbeMultiVcEnable[i] = config->PseTsnGbeMultiVcEnable[i]; |
| 135 | params->PseTsnGbeSgmiiEnable[i] = config->PseTsnGbeSgmiiEnable[i]; |
| 136 | params->PseTsnGbePhyInterfaceType[i] = |
Lean Sheng Tan | 100514d | 2022-05-18 17:35:31 +0200 | [diff] [blame] | 137 | !config->PseTsnGbeSgmiiEnable[i] ? |
Lean Sheng Tan | 7760fe4 | 2021-07-27 04:28:20 -0700 | [diff] [blame] | 138 | RGMII : config->PseTsnGbePhyType[i]; |
| 139 | params->PseTsnGbeLinkSpeed[i] = |
| 140 | (params->PseTsnGbePhyInterfaceType[i] < SGMII_plus) ? |
| 141 | xtal_freq_enum + 1 : xtal_freq_enum; |
| 142 | } |
| 143 | } |
| 144 | } |
| 145 | |
Lean Sheng Tan | 5cd7579 | 2021-06-09 13:58:12 -0700 | [diff] [blame] | 146 | static void fill_fsps_pse_params(FSP_S_CONFIG *params, |
| 147 | const struct soc_intel_elkhartlake_config *config) |
| 148 | { |
| 149 | static char psefwbuf[(CONFIG_PSE_FW_FILE_SIZE_KIB + |
| 150 | CONFIG_PSE_CONFIG_BUFFER_SIZE_KIB) * KiB]; |
| 151 | uint32_t pse_fw_base; |
| 152 | size_t psefwsize = cbfs_load("pse.bin", psefwbuf, sizeof(psefwbuf)); |
| 153 | if (psefwsize > 0) { |
| 154 | pse_fw_base = (uintptr_t)&psefwbuf; |
| 155 | params->SiipRegionBase = pse_fw_base; |
| 156 | params->SiipRegionSize = psefwsize; |
| 157 | printk(BIOS_DEBUG, "PSE base: %08x size: %08zx\n", pse_fw_base, psefwsize); |
| 158 | |
| 159 | /* Configure PSE peripherals */ |
| 160 | FSP_ARRAY_LOAD(params->PchPseDmaEnable, config->PseDmaOwn); |
| 161 | FSP_ARRAY_LOAD(params->PchPseDmaSbInterruptEnable, config->PseDmaSbIntEn); |
| 162 | FSP_ARRAY_LOAD(params->PchPseUartEnable, config->PseUartOwn); |
| 163 | FSP_ARRAY_LOAD(params->PchPseUartSbInterruptEnable, config->PseUartSbIntEn); |
| 164 | FSP_ARRAY_LOAD(params->PchPseHsuartEnable, config->PseHsuartOwn); |
| 165 | FSP_ARRAY_LOAD(params->PchPseQepEnable, config->PseQepOwn); |
| 166 | FSP_ARRAY_LOAD(params->PchPseQepSbInterruptEnable, config->PseQepSbIntEn); |
| 167 | FSP_ARRAY_LOAD(params->PchPseI2cEnable, config->PseI2cOwn); |
| 168 | FSP_ARRAY_LOAD(params->PchPseI2cSbInterruptEnable, config->PseI2cSbIntEn); |
| 169 | FSP_ARRAY_LOAD(params->PchPseI2sEnable, config->PseI2sOwn); |
| 170 | FSP_ARRAY_LOAD(params->PchPseI2sSbInterruptEnable, config->PseI2sSbIntEn); |
| 171 | FSP_ARRAY_LOAD(params->PchPseSpiEnable, config->PseSpiOwn); |
| 172 | FSP_ARRAY_LOAD(params->PchPseSpiSbInterruptEnable, config->PseSpiSbIntEn); |
| 173 | FSP_ARRAY_LOAD(params->PchPseSpiCs0Enable, config->PseSpiCs0Own); |
| 174 | FSP_ARRAY_LOAD(params->PchPseSpiCs1Enable, config->PseSpiCs1Own); |
| 175 | FSP_ARRAY_LOAD(params->PchPseCanEnable, config->PseCanOwn); |
| 176 | FSP_ARRAY_LOAD(params->PchPseCanSbInterruptEnable, config->PseCanSbIntEn); |
| 177 | params->PchPsePwmEnable = config->PsePwmOwn; |
| 178 | params->PchPsePwmSbInterruptEnable = config->PsePwmSbIntEn; |
| 179 | FSP_ARRAY_LOAD(params->PchPsePwmPinEnable, config->PsePwmPinEn); |
| 180 | params->PchPseAdcEnable = config->PseAdcOwn; |
| 181 | params->PchPseAdcSbInterruptEnable = config->PseAdcSbIntEn; |
| 182 | params->PchPseLh2PseSbInterruptEnable = config->PseLh2PseSbIntEn; |
| 183 | params->PchPseShellEnabled = config->PseShellEn; |
| 184 | |
| 185 | /* |
| 186 | * As a minimum requirement for PSE initialization, the configuration |
| 187 | * of devices below are required as shown. |
| 188 | * TODO: Help needed to find a better way to handle this part of code |
| 189 | * as the settings from devicetree are overwritten here. |
| 190 | * |
| 191 | * Set the ownership of these devices to PSE. These are hardcoded for now, |
| 192 | * if the PSE should be opened one day (hopefully), this can be handled |
| 193 | * much better. |
| 194 | */ |
| 195 | params->PchPseDmaEnable[0] = PSE_Owned; |
| 196 | params->PchPseUartEnable[2] = PSE_Owned; |
| 197 | params->PchPseHsuartEnable[2] = PSE_Owned; |
| 198 | params->PchPseI2cEnable[2] = PSE_Owned; |
| 199 | params->PchPseTimedGpioEnable[0] = PSE_Owned; |
| 200 | params->PchPseTimedGpioEnable[1] = PSE_Owned; |
| 201 | /* Disable PSE DMA Sideband Interrupt for DMA 0 */ |
| 202 | params->PchPseDmaSbInterruptEnable[0] = 0; |
| 203 | /* Set the log output to PSE UART 2 */ |
| 204 | params->PchPseLogOutputChannel = 3; |
| 205 | } else { |
| 206 | die("PSE enabled but PSE FW not available!\n"); |
| 207 | } |
| 208 | } |
| 209 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 210 | static void parse_devicetree(FSP_S_CONFIG *params) |
| 211 | { |
Tan, Lean Sheng | 09133c7 | 2021-05-26 06:40:56 -0700 | [diff] [blame] | 212 | const struct soc_intel_elkhartlake_config *config = config_of_soc(); |
| 213 | |
| 214 | /* LPSS controllers configuration */ |
| 215 | |
| 216 | /* I2C */ |
Lean Sheng Tan | 8bbff1f | 2021-06-15 22:05:42 -0700 | [diff] [blame] | 217 | FSP_ARRAY_LOAD(params->SerialIoI2cMode, config->SerialIoI2cMode); |
| 218 | FSP_ARRAY_LOAD(params->PchSerialIoI2cPadsTermination, |
| 219 | config->SerialIoI2cPadsTermination); |
Tan, Lean Sheng | 09133c7 | 2021-05-26 06:40:56 -0700 | [diff] [blame] | 220 | |
| 221 | params->PchSerialIoI2cSclPinMux[4] = 0x1B44AC09; //GPIO native mode for GPP_H9 |
| 222 | params->PchSerialIoI2cSdaPinMux[4] = 0x1B44CC08; //GPIO native mode for GPP_H8 |
| 223 | |
| 224 | /* GSPI */ |
Lean Sheng Tan | 8bbff1f | 2021-06-15 22:05:42 -0700 | [diff] [blame] | 225 | FSP_ARRAY_LOAD(params->SerialIoSpiMode, config->SerialIoGSpiMode); |
| 226 | FSP_ARRAY_LOAD(params->SerialIoSpiCsEnable, config->SerialIoGSpiCsEnable); |
| 227 | FSP_ARRAY_LOAD(params->SerialIoSpiCsMode, config->SerialIoGSpiCsMode); |
| 228 | FSP_ARRAY_LOAD(params->SerialIoSpiCsState, config->SerialIoGSpiCsState); |
Tan, Lean Sheng | 09133c7 | 2021-05-26 06:40:56 -0700 | [diff] [blame] | 229 | params->SerialIoSpiCsPolarity[2] = 0; |
| 230 | |
| 231 | /* UART */ |
Lean Sheng Tan | 8bbff1f | 2021-06-15 22:05:42 -0700 | [diff] [blame] | 232 | FSP_ARRAY_LOAD(params->SerialIoUartMode, config->SerialIoUartMode); |
| 233 | FSP_ARRAY_LOAD(params->SerialIoUartDmaEnable, config->SerialIoUartDmaEnable); |
Tan, Lean Sheng | 09133c7 | 2021-05-26 06:40:56 -0700 | [diff] [blame] | 234 | |
| 235 | params->SerialIoUartCtsPinMuxPolicy[0] = 0x2B01320F; //GPIO native mode for GPP_T15 |
| 236 | params->SerialIoUartRtsPinMuxPolicy[0] = 0x2B01220E; //GPIO native mode for GPP_T14 |
| 237 | params->SerialIoUartRxPinMuxPolicy[0] = 0x2B01020C; //GPIO native mode for GPP_T12 |
| 238 | params->SerialIoUartTxPinMuxPolicy[0] = 0x2B01120D; //GPIO native mode for GPP_T13 |
| 239 | |
| 240 | /* Provide correct UART number for FSP debug logs */ |
| 241 | params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 242 | } |
| 243 | |
| 244 | /* UPD parameters to be initialized before SiliconInit */ |
| 245 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 246 | { |
Lean Sheng Tan | 9420e28 | 2021-05-27 22:48:33 -0700 | [diff] [blame] | 247 | unsigned int i; |
Subrata Banik | 194f0eb | 2021-06-21 19:27:55 +0530 | [diff] [blame] | 248 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 249 | FSP_S_CONFIG *params = &supd->FspsConfig; |
Lean Sheng Tan | e9ee439 | 2021-05-26 08:11:51 -0700 | [diff] [blame] | 250 | struct soc_intel_elkhartlake_config *config = config_of_soc(); |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 251 | |
| 252 | /* Parse device tree and fill in FSP UPDs */ |
| 253 | parse_devicetree(params); |
| 254 | |
Lean Sheng Tan | e9ee439 | 2021-05-26 08:11:51 -0700 | [diff] [blame] | 255 | /* Load VBT before devicetree-specific config. */ |
| 256 | params->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
| 257 | |
| 258 | /* Check if IGD is present and fill Graphics init param accordingly */ |
Subrata Banik | 5b81b88 | 2021-06-09 03:59:11 +0530 | [diff] [blame] | 259 | params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); |
Lean Sheng Tan | e9ee439 | 2021-05-26 08:11:51 -0700 | [diff] [blame] | 260 | |
| 261 | /* Display config */ |
| 262 | params->DdiPortAHpd = config->DdiPortAHpd; |
| 263 | params->DdiPortADdc = config->DdiPortADdc; |
| 264 | params->DdiPortCHpd = config->DdiPortCHpd; |
| 265 | params->DdiPortCDdc = config->DdiPortCDdc; |
| 266 | |
Uwe Poeche | e9b417c | 2022-04-04 15:10:28 +0200 | [diff] [blame] | 267 | /* Intel Speed Step */ |
| 268 | params->Eist = config->eist_enable; |
| 269 | |
Lean Sheng Tan | e9ee439 | 2021-05-26 08:11:51 -0700 | [diff] [blame] | 270 | /* Use coreboot MP PPI services if Kconfig is enabled */ |
| 271 | if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) |
| 272 | params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); |
| 273 | |
| 274 | /* Chipset Lockdown */ |
| 275 | if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { |
| 276 | params->PchLockDownGlobalSmi = 0; |
| 277 | params->PchLockDownBiosLock = 0; |
| 278 | params->PchLockDownBiosInterface = 0; |
| 279 | params->PchWriteProtectionEnable[0] = 0; |
| 280 | params->PchUnlockGpioPads = 1; |
| 281 | params->RtcMemoryLock = 0; |
Tim Wawrzynczak | 26a77eb | 2021-08-26 09:20:44 -0600 | [diff] [blame] | 282 | params->SkipPamLock = 1; |
Lean Sheng Tan | e9ee439 | 2021-05-26 08:11:51 -0700 | [diff] [blame] | 283 | } else { |
| 284 | params->PchLockDownGlobalSmi = 1; |
| 285 | params->PchLockDownBiosLock = 1; |
| 286 | params->PchLockDownBiosInterface = 1; |
| 287 | params->PchWriteProtectionEnable[0] = 1; |
| 288 | params->PchUnlockGpioPads = 0; |
| 289 | params->RtcMemoryLock = 1; |
Tim Wawrzynczak | 26a77eb | 2021-08-26 09:20:44 -0600 | [diff] [blame] | 290 | params->SkipPamLock = 0; |
Lean Sheng Tan | e9ee439 | 2021-05-26 08:11:51 -0700 | [diff] [blame] | 291 | } |
| 292 | |
| 293 | /* Disable PAVP */ |
| 294 | params->PavpEnable = 0; |
| 295 | |
| 296 | /* Legacy 8254 timer support */ |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 297 | bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); |
| 298 | params->Enable8254ClockGating = !use_8254; |
Lean Sheng Tan | e9ee439 | 2021-05-26 08:11:51 -0700 | [diff] [blame] | 299 | params->Enable8254ClockGatingOnS3 = 1; |
| 300 | |
Michael Niewöhner | 0e90580 | 2021-09-25 00:10:30 +0200 | [diff] [blame] | 301 | /* |
| 302 | * Legacy PM ACPI Timer (and TCO Timer) |
| 303 | * This *must* be 1 in any case to keep FSP from |
| 304 | * 1) enabling PM ACPI Timer emulation in uCode. |
| 305 | * 2) disabling the PM ACPI Timer. |
| 306 | * We handle both by ourself! |
| 307 | */ |
| 308 | params->EnableTcoTimer = 1; |
| 309 | |
Lean Sheng Tan | e9ee439 | 2021-05-26 08:11:51 -0700 | [diff] [blame] | 310 | /* PCH Master Gating Control */ |
| 311 | params->PchPostMasterClockGating = 1; |
| 312 | params->PchPostMasterPowerGating = 1; |
| 313 | |
| 314 | /* HECI */ |
| 315 | params->Heci3Enabled = config->Heci3Enable; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 316 | |
Lean Sheng Tan | 9420e28 | 2021-05-27 22:48:33 -0700 | [diff] [blame] | 317 | /* USB configuration */ |
| 318 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
| 319 | params->PortUsb20Enable[i] = config->usb2_ports[i].enable; |
| 320 | params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; |
| 321 | params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; |
| 322 | params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; |
| 323 | params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; |
| 324 | params->Usb2OverCurrentPin[i] = config->usb2_ports[i].enable ? |
| 325 | config->usb2_ports[i].ocpin : 0xff; |
| 326 | } |
| 327 | |
| 328 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
| 329 | params->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
| 330 | params->Usb3OverCurrentPin[i] = config->usb3_ports[i].enable ? |
| 331 | config->usb3_ports[i].ocpin : 0xff; |
| 332 | if (config->usb3_ports[i].tx_de_emp) { |
| 333 | params->Usb3HsioTxDeEmphEnable[i] = 1; |
| 334 | params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; |
| 335 | } |
| 336 | if (config->usb3_ports[i].tx_downscale_amp) { |
| 337 | params->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 338 | params->Usb3HsioTxDownscaleAmp[i] = |
| 339 | config->usb3_ports[i].tx_downscale_amp; |
| 340 | } |
| 341 | } |
| 342 | |
| 343 | params->UsbClockGatingEnable = 1; |
| 344 | params->UsbPowerGatingEnable = 1; |
| 345 | |
Angel Pons | c7cfe0b | 2021-06-23 12:39:22 +0200 | [diff] [blame] | 346 | params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG); |
Lean Sheng Tan | 9420e28 | 2021-05-27 22:48:33 -0700 | [diff] [blame] | 347 | |
| 348 | /* PCIe root ports config */ |
| 349 | for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { |
| 350 | params->PcieRpClkReqDetect[i] = |
| 351 | !config->PcieRpClkReqDetectDisable[i]; |
| 352 | params->PcieRpL1Substates[i] = |
| 353 | get_l1_substate_control(config->PcieRpL1Substates[i]); |
| 354 | params->PcieRpLtrEnable[i] = !config->PcieRpLtrDisable[i]; |
| 355 | params->PcieRpAdvancedErrorReporting[i] = |
| 356 | !config->PcieRpAdvancedErrorReportingDisable[i]; |
| 357 | params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; |
| 358 | params->PciePtm[i] = config->PciePtm[i]; |
| 359 | params->PcieRpLtrMaxNoSnoopLatency[i] = 0x1003; |
| 360 | params->PcieRpLtrMaxSnoopLatency[i] = 0x1003; |
| 361 | /* Virtual Channel 1 to Traffic Class mapping */ |
| 362 | params->PcieRpVc1TcMap[i] = 0x60; |
| 363 | } |
| 364 | |
Lean Sheng Tan | c6c5443 | 2021-05-30 09:08:35 -0700 | [diff] [blame] | 365 | /* SATA config */ |
Subrata Banik | 5b81b88 | 2021-06-09 03:59:11 +0530 | [diff] [blame] | 366 | params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA); |
Lean Sheng Tan | c6c5443 | 2021-05-30 09:08:35 -0700 | [diff] [blame] | 367 | if (params->SataEnable) { |
| 368 | params->SataMode = config->SataMode; |
| 369 | params->SataSalpSupport = config->SataSalpSupport; |
| 370 | params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); |
| 371 | |
| 372 | for (i = 0; i < CONFIG_MAX_SATA_PORTS; i++) { |
| 373 | params->SataPortsEnable[i] = config->SataPortsEnable[i]; |
| 374 | params->SataPortsDevSlp[i] = config->SataPortsDevSlp[i]; |
| 375 | if (config->SataPortsEnableDitoConfig[i]) { |
| 376 | params->SataPortsDmVal[i] = |
| 377 | config->SataPortsDmVal[i] ? : DEF_DMVAL; |
| 378 | params->SataPortsDitoVal[i] = |
| 379 | config->SataPortsDitoVal[i] ? : DEF_DITOVAL_MS; |
| 380 | } |
| 381 | } |
| 382 | } |
| 383 | |
| 384 | /* SDCard config */ |
Subrata Banik | 5b81b88 | 2021-06-09 03:59:11 +0530 | [diff] [blame] | 385 | params->ScsSdCardEnabled = is_devfn_enabled(PCH_DEVFN_SDCARD); |
Lean Sheng Tan | c6c5443 | 2021-05-30 09:08:35 -0700 | [diff] [blame] | 386 | if (params->ScsSdCardEnabled) { |
| 387 | params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh; |
| 388 | params->SdCardGpioCmdPadTermination = GPIO_TERM_NATIVE; |
| 389 | params->SdCardGpioDataPadTermination[0] = GPIO_TERM_NATIVE; |
| 390 | params->SdCardGpioDataPadTermination[1] = GPIO_TERM_NATIVE; |
| 391 | params->SdCardGpioDataPadTermination[2] = GPIO_TERM_NATIVE; |
| 392 | params->SdCardGpioDataPadTermination[3] = GPIO_TERM_NATIVE; |
| 393 | } |
| 394 | |
| 395 | /* eMMC config */ |
Subrata Banik | 5b81b88 | 2021-06-09 03:59:11 +0530 | [diff] [blame] | 396 | params->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC); |
Lean Sheng Tan | c6c5443 | 2021-05-30 09:08:35 -0700 | [diff] [blame] | 397 | if (params->ScsEmmcEnabled) { |
| 398 | params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; |
| 399 | params->ScsEmmcDdr50Enabled = config->ScsEmmcDdr50Enabled; |
| 400 | } |
| 401 | |
Lean Sheng Tan | a96be27 | 2021-06-08 21:41:42 -0700 | [diff] [blame] | 402 | /* Thermal config */ |
Subrata Banik | 194f0eb | 2021-06-21 19:27:55 +0530 | [diff] [blame] | 403 | params->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF); |
Lean Sheng Tan | a96be27 | 2021-06-08 21:41:42 -0700 | [diff] [blame] | 404 | params->ProcHotResponse = 0x0; //Disable PROCHOT response |
| 405 | /* Thermal sensor (TS) target width */ |
| 406 | params->DmiTS0TW = 3; |
| 407 | params->DmiTS1TW = 2; |
| 408 | params->DmiTS2TW = 1; |
| 409 | /* Enable memory thermal throttling by default */ |
| 410 | if (!config->MemoryThermalThrottlingDisable) { |
| 411 | params->PchMemoryPmsyncEnable[0] = 1; |
| 412 | params->PchMemoryPmsyncEnable[1] = 1; |
| 413 | params->PchMemoryC0TransmitEnable[0] = 1; |
| 414 | params->PchMemoryC0TransmitEnable[1] = 1; |
| 415 | } |
| 416 | |
| 417 | /* TccActivationOffset config */ |
| 418 | params->TccActivationOffset = config->tcc_offset; |
| 419 | params->TccOffsetClamp = config->tcc_offset_clamp; |
| 420 | params->TccOffsetLock = 0x1; //lock Tcc Offset register |
| 421 | |
| 422 | /* Power management config */ |
| 423 | params->ImonSlope[0] = IMON_SLOPE; |
| 424 | params->ImonOffset[0] = IMON_OFFSET; |
| 425 | params->TdcCurrentLimit[0] = TDC_CURRENT_LIMIT_MAX; |
| 426 | params->AcLoadline[0] = AC_LOADLINE_LANE_0_MAX; |
| 427 | params->DcLoadline[0] = DC_LOADLINE_LANE_0_MAX; |
| 428 | params->AcLoadline[1] = AC_LOADLINE_LANE_1_MAX; |
| 429 | params->DcLoadline[1] = DC_LOADLINE_LANE_1_MAX; |
| 430 | params->IccMax[0] = ICC_LIMIT_MAX; |
| 431 | params->OneCoreRatioLimit = CORE_RATIO_LIMIT; |
| 432 | params->TwoCoreRatioLimit = CORE_RATIO_LIMIT; |
| 433 | params->ThreeCoreRatioLimit = CORE_RATIO_LIMIT; |
| 434 | params->FourCoreRatioLimit = CORE_RATIO_LIMIT; |
| 435 | params->FiveCoreRatioLimit = CORE_RATIO_LIMIT; |
| 436 | params->SixCoreRatioLimit = CORE_RATIO_LIMIT; |
| 437 | params->SevenCoreRatioLimit = CORE_RATIO_LIMIT; |
| 438 | params->EightCoreRatioLimit = CORE_RATIO_LIMIT; |
| 439 | params->PsysPmax = 0; //Set max platform power to auto profile |
| 440 | params->Custom1TurboActivationRatio = 0; |
| 441 | params->Custom2TurboActivationRatio = 0; |
| 442 | params->Custom3TurboActivationRatio = 0; |
| 443 | params->PchPwrOptEnable = 0x1; //Enable PCH DMI Power Optimizer |
| 444 | params->TStates = 0x0; //Disable T state |
| 445 | params->PkgCStateLimit = 0x7; //Set C state limit to C9 |
| 446 | params->FastPkgCRampDisable[0] = 0x1; |
| 447 | params->SlowSlewRate[0] = 0x1; |
| 448 | params->MaxRatio = 0x8; //Set max P state ratio |
| 449 | params->PchEspiLgmrEnable = 0; |
| 450 | params->PchPmPwrBtnOverridePeriod = config->PchPmPwrBtnOverridePeriod; |
| 451 | params->PchS0ixAutoDemotion = 0; |
| 452 | params->PmcV1p05PhyExtFetControlEn = 0x1; |
| 453 | params->PmcV1p05IsExtFetControlEn = 0x1; |
| 454 | /* FIVR config */ |
Lean Sheng Tan | 8d4e67d | 2021-06-25 11:23:03 -0700 | [diff] [blame] | 455 | if (config->fivr.fivr_config_en) { |
| 456 | fill_fsps_fivr_params(params, config); |
| 457 | } |
Lean Sheng Tan | a96be27 | 2021-06-08 21:41:42 -0700 | [diff] [blame] | 458 | |
Lean Sheng Tan | 0cdcdc7 | 2021-06-08 23:41:15 -0700 | [diff] [blame] | 459 | /* FuSa (Functional Safety) config */ |
| 460 | if (!config->FuSaEnable) { |
| 461 | params->DisplayFusaConfigEnable = 0; |
| 462 | params->GraphicFusaConfigEnable = 0; |
| 463 | params->OpioFusaConfigEnable = 0; |
| 464 | params->PsfFusaConfigEnable = 0; |
| 465 | } |
| 466 | |
Lean Sheng Tan | 5cd7579 | 2021-06-09 13:58:12 -0700 | [diff] [blame] | 467 | /* PSE (Intel Programmable Services Engine) config */ |
| 468 | if (CONFIG(PSE_ENABLE) && cbfs_file_exists("pse.bin")) |
| 469 | fill_fsps_pse_params(params, config); |
| 470 | |
Lean Sheng Tan | 7760fe4 | 2021-07-27 04:28:20 -0700 | [diff] [blame] | 471 | /* TSN GBE config */ |
| 472 | fill_fsps_tsn_params(params, config); |
| 473 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 474 | /* Override/Fill FSP Silicon Param for mainboard */ |
| 475 | mainboard_silicon_init_params(params); |
| 476 | } |
| 477 | |
| 478 | /* Mainboard GPIO Configuration */ |
| 479 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
| 480 | { |
| 481 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 482 | } |