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review.coreboot.org / coreboot / 27d6299d51744bda549b7764b8fde909ad812e33 / . / src / soc / intel / cannonlake / spi.c
blob: 8fd3126deea6fc611674d08e59a9e47c71bd35ee [file] [log] [blame]
Patrick Georgiac959032020-05-05 22:49:26 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-or-later */
Lijian Zhao32111172017-08-16 11:40:03 -0700[diff] [blame]2
Subrata Banik09564fc2017-11-09 12:16:36 +0530[diff] [blame]3#include <intelblocks/spi.h>
Lijian Zhao32111172017-08-16 11:40:03 -0700[diff] [blame]4#include <soc/pci_devs.h>
Lijian Zhao32111172017-08-16 11:40:03 -0700[diff] [blame]5
Subrata Banik09564fc2017-11-09 12:16:36 +0530[diff] [blame]6int spi_soc_devfn_to_bus(unsigned int devfn)
7{
8 switch (devfn) {
9 case PCH_DEVFN_SPI:
10 return 0;
11 case PCH_DEVFN_GSPI0:
12 return 1;
13 case PCH_DEVFN_GSPI1:
14 return 2;
15 case PCH_DEVFN_GSPI2:
16 return 3;
17 }
18 return -1;
19}