Michael Niewöhner | c4f8fbd | 2020-12-19 14:11:32 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <commonlib/helpers.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/mmio.h> |
| 6 | #include <device/pci_def.h> |
| 7 | #include <device/resource.h> |
| 8 | #include <drivers/intel/gma/i915_reg.h> |
| 9 | #include <intelblocks/graphics.h> |
| 10 | #include <soc/ramstage.h> |
| 11 | #include <types.h> |
| 12 | |
| 13 | void graphics_soc_panel_init(struct device *dev) |
| 14 | { |
| 15 | const struct soc_intel_cannonlake_config *conf = dev->chip_info; |
| 16 | const struct i915_gpu_panel_config *panel_cfg; |
| 17 | const struct resource *mmio_res; |
| 18 | void *mmio; |
| 19 | uint32_t reg32; |
| 20 | unsigned int pwm_period, pwm_polarity, pwm_duty; |
| 21 | |
| 22 | if (!conf) |
| 23 | return; |
| 24 | |
| 25 | panel_cfg = &conf->panel_cfg; |
| 26 | |
| 27 | mmio_res = probe_resource(dev, PCI_BASE_ADDRESS_0); |
| 28 | if (!mmio_res || !mmio_res->base) |
| 29 | return; |
| 30 | mmio = (void *)(uintptr_t)mmio_res->base; |
| 31 | |
| 32 | /* Panel timings */ |
| 33 | |
| 34 | reg32 = ((DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f) << 4; |
| 35 | reg32 |= PANEL_POWER_RESET; |
| 36 | write32(mmio + PCH_PP_CONTROL, reg32); |
| 37 | |
| 38 | reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16; |
| 39 | reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff; |
| 40 | write32(mmio + PCH_PP_ON_DELAYS, reg32); |
| 41 | |
| 42 | reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16; |
| 43 | reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff; |
| 44 | write32(mmio + PCH_PP_OFF_DELAYS, reg32); |
| 45 | |
| 46 | /* Backlight */ |
| 47 | if (panel_cfg->backlight_pwm_hz) { |
| 48 | pwm_polarity = panel_cfg->backlight_polarity ? BXT_BLC_PWM_POLARITY : 0; |
| 49 | pwm_period = DIV_ROUND_CLOSEST(CONFIG_CPU_XTAL_HZ, panel_cfg->backlight_pwm_hz); |
| 50 | pwm_duty = DIV_ROUND_CLOSEST(pwm_period, 2); /* Start with 50 % */ |
| 51 | |
| 52 | write32(mmio + BXT_BLC_PWM_FREQ(0), pwm_period); |
| 53 | write32(mmio + BXT_BLC_PWM_CTL(0), pwm_polarity); |
| 54 | write32(mmio + BXT_BLC_PWM_DUTY(0), pwm_duty); |
| 55 | } |
| 56 | } |
| 57 | |
| 58 | const struct i915_gpu_controller_info * |
| 59 | intel_igd_get_controller_info(const struct device *const dev) |
| 60 | { |
| 61 | const struct soc_intel_cannonlake_config *const chip = dev->chip_info; |
| 62 | return &chip->gfx; |
| 63 | } |