Angel Pons | f5627e8 | 2020-04-05 15:46:52 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/pci.h> |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 5 | #include <cpu/x86/mp.h> |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 6 | #include <cpu/x86/msr.h> |
Kyösti Mälkki | faf20d3 | 2019-08-14 05:41:41 +0300 | [diff] [blame] | 7 | #include <cpu/intel/smm_reloc.h> |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 8 | #include <cpu/intel/turbo.h> |
| 9 | #include <intelblocks/cpulib.h> |
| 10 | #include <intelblocks/mp_init.h> |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 11 | #include <soc/cpu.h> |
| 12 | #include <soc/msr.h> |
| 13 | #include <soc/pci_devs.h> |
Sumeet Pawnikar | c896e92e | 2019-01-08 19:52:54 +0530 | [diff] [blame] | 14 | #include <soc/systemagent.h> |
Ronak Kanabar | 69a9565 | 2019-02-19 20:10:23 +0530 | [diff] [blame] | 15 | #include <cpu/x86/mtrr.h> |
| 16 | #include <cpu/intel/microcode.h> |
Ronak Kanabar | a432f38 | 2019-03-16 21:26:43 +0530 | [diff] [blame] | 17 | #include <cpu/intel/common/common.h> |
Felix Held | d27ef5b | 2021-10-20 20:18:12 +0200 | [diff] [blame] | 18 | #include <types.h> |
Sumeet Pawnikar | c896e92e | 2019-01-08 19:52:54 +0530 | [diff] [blame] | 19 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 20 | #include "chip.h" |
| 21 | |
Subrata Banik | 56ab8e2 | 2022-01-07 13:40:19 +0000 | [diff] [blame] | 22 | bool cpu_soc_is_in_untrusted_mode(void) |
| 23 | { |
| 24 | msr_t msr; |
| 25 | |
| 26 | msr = rdmsr(MSR_BIOS_DONE); |
| 27 | return !!(msr.lo & ENABLE_IA_UNTRUSTED); |
| 28 | } |
| 29 | |
Subrata Banik | 37a55d1 | 2022-05-30 18:11:12 +0000 | [diff] [blame] | 30 | void cpu_soc_bios_done(void) |
| 31 | { |
| 32 | msr_t msr; |
| 33 | |
| 34 | msr = rdmsr(MSR_BIOS_DONE); |
| 35 | msr.lo |= ENABLE_IA_UNTRUSTED; |
| 36 | wrmsr(MSR_BIOS_DONE, msr); |
| 37 | } |
| 38 | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 39 | static void soc_fsp_load(void) |
| 40 | { |
Kyösti Mälkki | cc93c6e | 2021-01-09 22:53:52 +0200 | [diff] [blame] | 41 | fsps_load(); |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 42 | } |
| 43 | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 44 | static void configure_misc(void) |
| 45 | { |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 46 | msr_t msr; |
| 47 | |
Angel Pons | bda02b0 | 2020-09-28 01:10:40 +0200 | [diff] [blame] | 48 | config_t *conf = config_of_soc(); |
| 49 | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 50 | msr = rdmsr(IA32_MISC_ENABLE); |
| 51 | msr.lo |= (1 << 0); /* Fast String enable */ |
| 52 | msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ |
Matt Delco | 54e9894 | 2020-03-09 12:41:09 -0700 | [diff] [blame] | 53 | wrmsr(IA32_MISC_ENABLE, msr); |
| 54 | |
Subrata Banik | 6d56916 | 2019-04-10 12:19:27 +0530 | [diff] [blame] | 55 | /* Set EIST status */ |
| 56 | cpu_set_eist(conf->eist_enable); |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 57 | |
| 58 | /* Disable Thermal interrupts */ |
| 59 | msr.lo = 0; |
| 60 | msr.hi = 0; |
| 61 | wrmsr(IA32_THERM_INTERRUPT, msr); |
| 62 | |
| 63 | /* Enable package critical interrupt only */ |
| 64 | msr.lo = 1 << 4; |
| 65 | msr.hi = 0; |
| 66 | wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); |
| 67 | |
| 68 | /* Enable PROCHOT */ |
| 69 | msr = rdmsr(MSR_POWER_CTL); |
Angel Pons | 4d794bd | 2021-10-11 14:00:54 +0200 | [diff] [blame] | 70 | msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ |
Angel Pons | a0f8dc3 | 2021-10-11 14:01:55 +0200 | [diff] [blame] | 71 | msr.lo |= (1 << 18); /* Enable Energy/Performance Bias control */ |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 72 | msr.lo |= (1 << 23); /* Lock it */ |
| 73 | wrmsr(MSR_POWER_CTL, msr); |
| 74 | } |
| 75 | |
Nico Huber | 234e7ec | 2021-07-27 10:26:31 +0000 | [diff] [blame] | 76 | static void configure_c_states(const config_t *const cfg) |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 77 | { |
| 78 | msr_t msr; |
| 79 | |
Nico Huber | 234e7ec | 2021-07-27 10:26:31 +0000 | [diff] [blame] | 80 | msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); |
| 81 | if (cfg->max_package_c_state && (msr.lo & 0xf) >= cfg->max_package_c_state) { |
| 82 | msr.lo = (msr.lo & ~0xf) | ((cfg->max_package_c_state - 1) & 0xf); |
Nico Huber | 234e7ec | 2021-07-27 10:26:31 +0000 | [diff] [blame] | 83 | } |
Angel Pons | 0c7a250 | 2021-10-11 13:53:15 +0200 | [diff] [blame] | 84 | msr.lo |= CST_CFG_LOCK_MASK; |
| 85 | wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); |
Nico Huber | 234e7ec | 2021-07-27 10:26:31 +0000 | [diff] [blame] | 86 | |
Nico Huber | 327c04a | 2021-07-26 13:34:59 +0000 | [diff] [blame] | 87 | /* C-state Interrupt Response Latency Control 0 - package C3 latency */ |
| 88 | msr.hi = 0; |
| 89 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT; |
| 90 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_0, msr); |
| 91 | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 92 | /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */ |
| 93 | msr.hi = 0; |
Nico Huber | 327c04a | 2021-07-26 13:34:59 +0000 | [diff] [blame] | 94 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 95 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr); |
| 96 | |
| 97 | /* C-state Interrupt Response Latency Control 2 - package C6/C7 long */ |
| 98 | msr.hi = 0; |
Nico Huber | 327c04a | 2021-07-26 13:34:59 +0000 | [diff] [blame] | 99 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 100 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); |
| 101 | |
| 102 | /* C-state Interrupt Response Latency Control 3 - package C8 */ |
| 103 | msr.hi = 0; |
Nico Huber | ad5b8b8 | 2021-07-26 13:43:24 +0000 | [diff] [blame] | 104 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT; |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 105 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); |
| 106 | |
| 107 | /* C-state Interrupt Response Latency Control 4 - package C9 */ |
| 108 | msr.hi = 0; |
Nico Huber | ad5b8b8 | 2021-07-26 13:43:24 +0000 | [diff] [blame] | 109 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT; |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 110 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); |
| 111 | |
| 112 | /* C-state Interrupt Response Latency Control 5 - package C10 */ |
| 113 | msr.hi = 0; |
Nico Huber | ad5b8b8 | 2021-07-26 13:43:24 +0000 | [diff] [blame] | 114 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT; |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 115 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); |
| 116 | } |
| 117 | |
| 118 | /* All CPUs including BSP will run the following function. */ |
Elyes HAOUAS | 3c8b5d0 | 2018-05-27 16:57:24 +0200 | [diff] [blame] | 119 | void soc_core_init(struct device *cpu) |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 120 | { |
Patrick Rudolph | e9b0830 | 2021-02-16 11:52:38 +0100 | [diff] [blame] | 121 | config_t *cfg = config_of_soc(); |
| 122 | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 123 | /* Clear out pending MCEs */ |
Pratik Prajapati | 2ad1ddb | 2017-08-28 12:28:24 -0700 | [diff] [blame] | 124 | /* TODO(adurbin): This should only be done on a cold boot. Also, some |
| 125 | * of these banks are core vs package scope. For now every CPU clears |
| 126 | * every bank. */ |
Subrata Banik | f91344c | 2019-05-06 19:23:26 +0530 | [diff] [blame] | 127 | mca_configure(); |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 128 | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 129 | enable_lapic_tpr(); |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 130 | |
| 131 | /* Configure c-state interrupt response time */ |
Nico Huber | 234e7ec | 2021-07-27 10:26:31 +0000 | [diff] [blame] | 132 | configure_c_states(cfg); |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 133 | |
| 134 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 135 | configure_misc(); |
| 136 | |
Michael Niewöhner | 5611cfd | 2020-10-11 13:04:02 +0200 | [diff] [blame] | 137 | set_aesni_lock(); |
| 138 | |
Lijian Zhao | 0f5d7b9 | 2018-10-05 10:31:11 -0700 | [diff] [blame] | 139 | enable_pm_timer_emulation(); |
| 140 | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 141 | /* Enable Direct Cache Access */ |
| 142 | configure_dca_cap(); |
| 143 | |
| 144 | /* Set energy policy */ |
| 145 | set_energy_perf_bias(ENERGY_POLICY_NORMAL); |
| 146 | |
Patrick Rudolph | e9b0830 | 2021-02-16 11:52:38 +0100 | [diff] [blame] | 147 | if (cfg->cpu_turbo_disable) |
| 148 | disable_turbo(); |
| 149 | else |
| 150 | enable_turbo(); |
Ronak Kanabar | a432f38 | 2019-03-16 21:26:43 +0530 | [diff] [blame] | 151 | |
| 152 | /* Enable Vmx */ |
Angel Pons | 67d0672 | 2022-01-31 17:41:29 +0100 | [diff] [blame] | 153 | set_feature_ctrl_vmx_arg(CONFIG(ENABLE_VMX) && !cfg->disable_vmx); |
| 154 | set_feature_ctrl_lock(); |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 155 | } |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 156 | |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 157 | static void per_cpu_smm_trigger(void) |
| 158 | { |
| 159 | /* Relocate the SMM handler. */ |
| 160 | smm_relocate(); |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 161 | } |
| 162 | |
Angel Pons | 1b8e65d | 2021-02-19 18:29:58 +0100 | [diff] [blame] | 163 | void smm_lock(void) |
| 164 | { |
| 165 | struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
| 166 | /* |
| 167 | * LOCK the SMM memory window and enable normal SMM. |
| 168 | * After running this function, only a full reset can |
| 169 | * make the SMM registers writable again. |
| 170 | */ |
| 171 | printk(BIOS_DEBUG, "Locking SMM.\n"); |
| 172 | pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); |
| 173 | } |
| 174 | |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 175 | static void post_mp_init(void) |
| 176 | { |
| 177 | /* Set Max Ratio */ |
| 178 | cpu_set_max_ratio(); |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 179 | |
| 180 | /* |
| 181 | * Now that all APs have been relocated as well as the BSP let SMIs |
| 182 | * start flowing. |
| 183 | */ |
Kyösti Mälkki | 040c531 | 2020-05-31 20:03:11 +0300 | [diff] [blame] | 184 | global_smi_enable_no_pwrbtn(); |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 185 | |
| 186 | /* Lock down the SMRAM space. */ |
| 187 | smm_lock(); |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 188 | } |
| 189 | |
| 190 | static const struct mp_ops mp_ops = { |
| 191 | /* |
| 192 | * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, |
| 193 | * that are set prior to ramstage. |
| 194 | * Real MTRRs programming are being done after resource allocation. |
| 195 | */ |
| 196 | .pre_mp_init = soc_fsp_load, |
| 197 | .get_cpu_count = get_cpu_count, |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 198 | .get_smm_info = smm_info, |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 199 | .get_microcode_info = get_microcode_info, |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 200 | .pre_mp_smm_init = smm_initialize, |
| 201 | .per_cpu_smm_trigger = per_cpu_smm_trigger, |
| 202 | .relocation_handler = smm_relocation_handler, |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 203 | .post_mp_init = post_mp_init, |
| 204 | }; |
| 205 | |
| 206 | void soc_init_cpus(struct bus *cpu_bus) |
| 207 | { |
Felix Held | 4dd7d11 | 2021-10-20 23:31:43 +0200 | [diff] [blame] | 208 | /* TODO: Handle mp_init_with_smm failure? */ |
| 209 | mp_init_with_smm(cpu_bus, &mp_ops); |
John Su | 3126964 | 2019-01-10 14:53:26 +0800 | [diff] [blame] | 210 | |
| 211 | /* Thermal throttle activation offset */ |
Sumeet R Pawnikar | 360684b | 2020-06-18 15:56:11 +0530 | [diff] [blame] | 212 | configure_tcc_thermal_target(); |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 213 | } |
Ronak Kanabar | 69a9565 | 2019-02-19 20:10:23 +0530 | [diff] [blame] | 214 | |
| 215 | int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) |
| 216 | { |
| 217 | msr_t msr1; |
| 218 | msr_t msr2; |
| 219 | |
| 220 | /* |
Ronak Kanabar | 69a9565 | 2019-02-19 20:10:23 +0530 | [diff] [blame] | 221 | * If PRMRR/SGX is supported the FIT microcode load will set the msr |
| 222 | * 0x08b with the Patch revision id one less than the id in the |
| 223 | * microcode binary. The PRMRR support is indicated in the MSR |
| 224 | * MTRRCAP[12]. If SGX is not enabled, check and avoid reloading the |
| 225 | * same microcode during CPU initialization. If SGX is enabled, as |
| 226 | * part of SGX BIOS initialization steps, the same microcode needs to |
| 227 | * be reloaded after the core PRMRR MSRs are programmed. |
| 228 | */ |
| 229 | msr1 = rdmsr(MTRR_CAP_MSR); |
| 230 | msr2 = rdmsr(MSR_PRMRR_PHYS_BASE); |
| 231 | if (msr2.lo && (current_patch_id == new_patch_id - 1)) |
| 232 | return 0; |
| 233 | |
Kyösti Mälkki | eadd251 | 2020-06-11 09:52:45 +0300 | [diff] [blame] | 234 | return (msr1.lo & MTRR_CAP_PRMRR) && |
Ronak Kanabar | 69a9565 | 2019-02-19 20:10:23 +0530 | [diff] [blame] | 235 | (current_patch_id == new_patch_id - 1); |
| 236 | } |