blob: 24c348ac1159d4eb3a18e1a6811b640c601a6ca5 [file] [log] [blame]
Subrata Banikb3ced6a2020-08-04 13:34:03 +05301ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE),y)
Subrata Banik292afef2020-09-09 13:34:18 +05302subdirs-y += romstage
3subdirs-y += ../../../cpu/intel/microcode
4subdirs-y += ../../../cpu/intel/turbo
Subrata Banik292afef2020-09-09 13:34:18 +05305
Subrata Banik2871e0e2020-09-27 11:30:58 +05306# all (bootblock, verstage, romstage, postcar, ramstage)
7all-y += gspi.c
8all-y += i2c.c
9all-y += pmutil.c
10all-y += spi.c
11all-y += uart.c
12
Subrata Banikb3ced6a2020-08-04 13:34:03 +053013bootblock-y += bootblock/bootblock.c
Subrata Banikb3ced6a2020-08-04 13:34:03 +053014bootblock-y += bootblock/pch.c
15bootblock-y += bootblock/report_platform.c
Subrata Banik292afef2020-09-09 13:34:18 +053016bootblock-y += espi.c
Subrata Banikaab8bb22020-09-21 16:03:43 +053017bootblock-y += gpio.c
Subrata Banik292afef2020-09-09 13:34:18 +053018bootblock-y += p2sb.c
Reka Normane790f922022-04-06 20:33:54 +100019bootblock-$(CONFIG_ALDERLAKE_CONFIGURE_DESCRIPTOR) += bootblock/update_descriptor.c
Subrata Banik292afef2020-09-09 13:34:18 +053020
21romstage-y += espi.c
Subrata Banikaab8bb22020-09-21 16:03:43 +053022romstage-y += gpio.c
Subrata Banik292afef2020-09-09 13:34:18 +053023romstage-y += meminit.c
Eric Laif8248f32020-12-31 11:43:29 +080024romstage-y += pcie_rp.c
Subrata Banik292afef2020-09-09 13:34:18 +053025romstage-y += reset.c
Tim Wawrzynczakb0d3a012021-12-02 16:19:29 -070026romstage-y += cpu.c
Subrata Banikaab8bb22020-09-21 16:03:43 +053027
Subrata Banik2871e0e2020-09-27 11:30:58 +053028ramstage-y += acpi.c
29ramstage-y += chip.c
30ramstage-y += cpu.c
Sumeet R Pawnikara2a90a32021-04-12 21:30:19 +053031ramstage-y += dptf.c
Subrata Banik2871e0e2020-09-27 11:30:58 +053032ramstage-y += elog.c
33ramstage-y += espi.c
34ramstage-y += finalize.c
35ramstage-y += fsp_params.c
Subrata Banikaab8bb22020-09-21 16:03:43 +053036ramstage-y += gpio.c
Subrata Banik2871e0e2020-09-27 11:30:58 +053037ramstage-y += lockdown.c
38ramstage-y += me.c
39ramstage-y += p2sb.c
Eric Laif8248f32020-12-31 11:43:29 +080040ramstage-y += pcie_rp.c
Subrata Banik2871e0e2020-09-27 11:30:58 +053041ramstage-y += pmc.c
42ramstage-y += reset.c
Michał Żygowski9df95d92022-04-08 17:02:35 +020043ramstage-$(CONFIG_SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT) += retimer.c
Subrata Banik2871e0e2020-09-27 11:30:58 +053044ramstage-y += soundwire.c
45ramstage-y += systemagent.c
John848b4252022-03-09 17:51:56 -080046ramstage-y += tcss.c
V Sowmyac6d71662021-07-15 08:11:08 +053047ramstage-y += vr_config.c
Tim Wawrzynczak291b58f2020-11-10 10:25:04 -070048ramstage-y += xhci.c
Francois Toguocea4f922021-04-16 21:20:39 -070049ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c
Subrata Banikaab8bb22020-09-21 16:03:43 +053050
Hsuan-ting Chen642508a2021-10-27 10:59:41 +000051verstage-y += gpio.c
52
Sugnan Prabhu Sf040f752021-03-26 10:58:49 +053053smm-y += elog.c
Subrata Banikaab8bb22020-09-21 16:03:43 +053054smm-y += gpio.c
Subrata Banik2871e0e2020-09-27 11:30:58 +053055smm-y += p2sb.c
56smm-y += pmutil.c
57smm-y += smihandler.c
58smm-y += uart.c
Sugnan Prabhu Sf040f752021-03-26 10:58:49 +053059smm-y += xhci.c
Subrata Banikaab8bb22020-09-21 16:03:43 +053060
Subrata Banikb3ced6a2020-08-04 13:34:03 +053061CPPFLAGS_common += -I$(src)/soc/intel/alderlake
62CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include
Furquan Shaikhf888c682021-10-05 21:37:33 -070063
64ifeq ($(CONFIG_STITCH_ME_BIN),y)
65
Bernardo Perez Priegoaba1c132021-10-20 21:13:29 -070066$(eval $(call cse_add_dummy_to_bp1_bp2,DLMP))
67$(eval $(call cse_add_dummy_to_bp1_bp2,IFPP))
68$(eval $(call cse_add_dummy_to_bp1_bp2,SBDT))
69$(eval $(call cse_add_decomp_to_bp1_bp2,RBEP))
70$(eval $(call cse_add_dummy_to_bp1_bp2,UFSP))
71$(eval $(call cse_add_dummy_to_bp1_bp2,UFSG))
Ravindra N07092182021-12-06 10:11:51 +053072$(eval $(call cse_add_input_to_bp1_bp2,OEMP))
Bernardo Perez Priegoaba1c132021-10-20 21:13:29 -070073$(eval $(call cse_add_input_to_bp1_bp2,PMCP))
74$(eval $(call cse_add_decomp,bp1,MFTP))
75$(eval $(call cse_add_decomp,bp2,FTPR))
76$(eval $(call cse_add_input_to_bp1_bp2,IOMP))
77$(eval $(call cse_add_input_to_bp1_bp2,NPHY))
78$(eval $(call cse_add_input_to_bp1_bp2,TBTP))
79$(eval $(call cse_add_input_to_bp1_bp2,PCHC))
80$(eval $(call cse_add_decomp,bp2,NFTP))
81$(eval $(call cse_add_dummy,bp2,ISHP))
82$(eval $(call cse_add_input,bp2,IUNP))
Furquan Shaikhf888c682021-10-05 21:37:33 -070083
84endif
85
Subrata Banikb3ced6a2020-08-04 13:34:03 +053086endif